What is dominant state in can

The CAN specifications use the terms "dominant" bits and "recessive" bits, where dominant is a logical 0 (actively driven to a voltage by the transmitter) and recessive is a logical 1 (passively returned to a voltage by a resistor). The idle state is represented by the recessive level (Logical 1).

What is dominant and recessive state in CAN?

Therefore, if two nodes begin to transmit simultaneously, the node that sends a last identifier bit as a zero (dominant) while the other nodes send a one (recessive) retains control of the CAN bus and goes on to complete its message. A dominant bit always overwrites a recessive bit on a CAN bus.

Which is dominant bit in CAN?

For CAN 2.0A, an 11-bit Identifier and one bit, the RTR bit, which is dominant for data frames. For CAN 2.0B, a 29-bit Identifier (which also contains two recessive bits: SRR and IDE) and the RTR bit.

CAN bus dominant level?

A CAN bus can have two bit states: dominant or recessive. If one node sends a dominant bit and another sends a recessive bit, the result will be dominant (as shown in Table 1).