What is miv_rv32?
8.1. 8.2. 9. The MIV_RV32 is a processor core designed to implement the RISC-V instruction set for use in Microchip FPGAs. The core includes the industry standard JTAG interface to facilitate debug access. Three optional bus interfaces are available for peripheral and memory accesses: AHB, APB3, and AXI, which can be configured as AXI3 or AXI4.
What bus interfaces are available in miv_rv32 libero®?
Three optional bus interfaces are available for peripheral and memory accesses: AHB, APB3, and AXI, which can be configured as AXI3 or AXI4. There are three dedicated interrupts as well as eight optional external interrupts in the MIV_RV32 processor core. A design guide is available describing how to create a MIV_RV32 Libero® design.
What is the default APB initiator address in mi-V RV32?
In the MIV_RV32, the default APB Initiator address is 0x7000_0000, which corresponds to the address shown in the following figure. Further details can be obtained from the Mi-V RV32 Design Guide provided with this core. The following figure shows the MIV_RV32 configuration settings for peripherals. Figure 8-3. RV32 Configurator Memory Map
Does miv_rv32 support AXI burst transactions?
Itshould be noted that MIV_RV32 does not feature an L1 cache and as such AXI burst transactions are not available.In this instance, careful consideration should be given before migrating to MIV_RV32 as performance with DDR willbe limited. Each peripheral connected to a Mi-V Legacy core has an APB interface and is connected to an APB bus.
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