What are the advantages of high-level synthesis?
The higher level (usually C based) representation enables algorithms to be expressed more easily, significantly reducing development times.
The higher level also makes design space exploration easier, making it easier to optimise the trade-off between resources and processing speed.What is high-level synthesis used for?
High level synthesis or HLS is a software tool that generates Verilog logic gates from C-like high-level code.
It allows the users who are not familiar with logic design to develop hardware accelerators for complex ML algorithms on FPGA.What are the limitations of high-level synthesis?
The main limitation of using HLS is that it does not re- move the need for hardware design.
If it is realised that the language is not software, but actually describing hardware, then it is possible to use the high level languages to also de- scribe relatively low level constructs where necessary.- The code writing process in a high-level language should follow not only the synthesis standard but also meet the timing requirements.
The function and interface specification should be implemented correctly.
The most common constraints are memory, interface, hierarchy, loop, timing, iteration, etc.
Shared CSD Complex Constant Multiplier for Parallel FFT Processors
Advanced constant multiplier for multipath pipelined FFT processor
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