VHDL is a hardware description language used to describe the structure and behaviour of digital electronic hardware designs, such as FPGAs and ASICs.
VHDL is an abbreviation of VHSIC (very high speed integrated circuit) Hardware Description Language.
This contains the implementation of a microprocessor and a Central Processing Unit(CPU) using Verilog Hardware Descriptive Language(VHDL).
The Field Programmable Gate Array(FPGA) contains logic components that can be programmed to perform a task.
To create a new project, select File > New > VHDL Project or File > New > Verilog Project.
Then give your project a name.
By default, the Use default location checkbox is checked, which means that new projects will be located in the workspace folder.