ARM Architecture Reference Manual Thumb-2 Supplement
The additions provide ARM equivalents of instructions supported in the Thumb instruction set. opcodes and locations of further information about the data ...
The Thumb instruction set
opcodes into ARM opcodes. r This means the effect of Thumb and ARM instructions are the same. – Thumb is more restricted
ARM and Thumb Instruction Encodings
op1 and op2 are the opcode extension fields in coprocessor instructions. post indicates a postindexed addressing mode such as [Rn] Rm or [Rn]
ARM® and Thumb®-2 Instruction Set Quick Reference Card
Thumb: a 32-bit constant formed by left-shifting an 8-bit value by any number of bits
ARM Instruction Set
The first operand is always a register (Rn). Cond. 00. I OpCode. Rn. Rd. Operand 2.
ARMv6-M Architecture Reference Manual
The Thumb Instruction Set Encoding. This chapter describes how the Thumb instruction set uses the ARM programmers' model. It contains the following sections
ARM Architecture Reference Manual Thumb-2 Supplement
ARM the ARM Powered logo
Thumb® 16-bit Instruction Set Quick Reference Card
This card lists all Thumb instructions available on Thumb-capable processors earlier than ARM®v6T2. In addition it lists all Thumb-2 16-bit instructions.
THUMB Instruction Set
ARM DDI 0029E. 5-1. 11. 1. Open Access. THUMB Instruction Set. This chapter describes the THUMB instruction set. Format Summary. 5-2. Opcode Summary.
The Thumb instruction set
opcodes into ARM opcodes. r This means the effect of Thumb and ARM instructions are the same. – Thumb is more restricted
ARM Architecture Reference Manual Thumb-2 Supplement
4 jun 2011 The additions provide ARM equivalents of instructions supported in the Thumb instruction set. The precise effects of each new instruction ...
ARMando el rompecabezas
Interpreta los opcodes según el estado (distinto set de instrucciones) Thumb es una compresión del set ARM para aumentar la densidad de.
ARM Instruction Set
the instruction stream will be decoded as ARM or THUMB instructions. Figure 4-2: Branch and Exchange instructions. 4.3.1 Instruction cycle times.
Introducción a la arquitectura de computadores con QtARMSim y
II Arquitectura ARM con QtARMSim. 2 Primeros pasos con ARM y QtARMSim. 2.1. Introducción al ensamblador Thumb de ARM. 2.2. Introducción al simulador
ARMando el rompecabezas
Interpreta los opcodes según el estado (distinto set de instrucciones) Thumb es una compresión del set ARM para aumentar la densidad de.
ARMv7-M Architecture Reference Manual
Details of the ARM architecture memory attributes and memory order model. Chapter A4 The ARMv7-M Instruction Set. General information on the Thumb®
ARM® and Thumb®-2 Instruction Set Quick Reference Card
ARM® and Thumb®-2 Instruction Set. Quick Reference Card. Key to Tables. Rm { <opsh>}. See Table Register
ARM Architecture Reference Manual
The Thumb instruction set is a re-encoded subset of the ARM instruction set. Thumb instructions execute in their own processor state with the architecture
ARM7TDMI Data Sheet
ARM DDI 0029E
5-1 11 1 Open AccessTHUMB Instruction SetThis chapter describes the THUMB instruction set.Format Summary 5-2
Opcode Summary 5-3
5.1 Format 1: move shifted register 5-5
5.2 Format 2: add/subtract 5-7
5.3 Format 3: move/compare/add/subtract immediate 5-9
5.4 Format 4: ALU operations 5-11
5.5 Format 5: Hi register operations/branch exchange 5-13
5.6 Format 6: PC-relative load 5-16
5.7 Format 7: load/store with register offset 5-18
5.8 Format 8: load/store sign-extended byte/halfword 5-20
5.9 Format 9: load/store with immediate offset 5-22
5.10 Format 10: load/store halfword 5-24
5.11 Format 11: SP-relative load/store 5-26
5.12 Format 12: load address 5-28
5.13 Format 13: add offset to Stack Pointer 5-30
5.14 Format 14: push/pop registers 5-32
5.15 Format 15: multiple load/store 5-34
5.16 Format 16: conditional branch 5-36
5.17 Format 17: software interrupt 5-38
5.18 Format 18: unconditional branch 5-39
5.19 Format 19: long branch with link 5-40
5.20 Instruction Set Examples 5-42
5THUMB Instruction Set
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Format Summary
The THUMB instruction set formats are shown in the following figure.Figure 5-1: THUMB instruction set formats
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
10 0 0 Op Offset5 Rs RdMove shifted register
20 0 0 1 1 I Op Rn/offset3 Rs RdAdd/subtract
30 0 1 Op Rd Offset8
Move/compare/add
/subtract immediate40 1 0 0 0 0 Op Rs Rd ALU operations50 1 0 0 0 1 Op H1 H2 Rs/Hs Rd/HdHi register operations /branch exchange60 1 0 0 1 Rd Word8PC-relative load
70 1 0 1 L B 0 Ro Rb RdLoad/store with register
offset80 1 0 1 H S 1 Ro Rb RdLoad/store sign-extended
byte/halfword90 1 1 B L Offset5 Rb RdLoad/store with immediate
offset101 0 0 0 L Offset5 Rb RdLoad/store halfword
111 0 0 1 L Rd Word8SP-relative load/store
121 0 1 0 SP Rd Word8Load address
131 0 1 1 0 0 0 0 S SWord7Add offset to stack pointer
141 0 1 1 L 1 0 R RlistPush/pop registers
151 1 0 0 L Rb RlistMultiple load/store
161 1 0 1 Cond Soffset8Conditional branch
171 1 0 1 1 1 1 1 Value8
Software Interrupt181 1 1 0 0 Offset11Unconditional branch191 1 1 1 H OffsetLong branch with link
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
THUMB Instruction Set
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Opcode Summary
The following table summarizes the THUMB instruction set. For further information about a particular instruction please refer to the sections listed in the right-most column.Mnemonic Instruction Lo register
operandHi register operandCondition codes setSee Section:ADCAdd with Carry445.4
ADD Add4 4 4À5.1.3, 5.5, 5.12, 5.13
ANDAND445.4
ASR Arithmetic Shift Right4 45.1, 5.4
BUnconditional branch45.16
B xxConditional branch45.17BICBit Clear445.4
BL Branch and Link 5.19
BXBranch and Exchange445.5
CMN Compare Negative4 45.4
CMPCompare4445.3, 5.4, 5.5
EOR EOR4 45.4
LDMIALoad multiple45.15
LDR Load word45.7, 5.6, 5.9, 5.11
LDRBLoad byte45.7, 5.9
LDRH Load halfword45.8, 5.10
LSLLogical Shift Left445.1, 5.4
LDSB Load sign-extended
byte45.8LDSHLoad sign-extended
halfword45.8LSR Logical Shift Right4 45.1, 5.4
MOVMove register444¡5.3, 5.5
MUL Multiply4 45.4
MVNMove Negative register445.4
Table 5-1: THUMB instruction set opcodes
THUMB Instruction Set
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ÀThe condition codes are unaffected by the format 5, 12 and 13 versions of this instruction. ÁThe condition codes are unaffected by the format 5 version of this instruction.NEG Negate4 45.4
ORROR445.4
POP Pop registers45.14
PUSHPush registers45.14
ROR Rotate Right4 45.4
SBCSubtract with Carry445.4
STMIA Store Multiple45.15
STRStore word45.7, 5.9, 5.11
STRB Store byte45.7
STRHStore halfword45.8, 5.10
SWI Software Interrupt 5.17
SUBSubtract445.1.3, 5.3
TST Test bits4 45.4Mnemonic Instruction Lo register operandHi register operandCondition codes setSee Section: Table 5-1: THUMB instruction set opcodes (Continued)THUMB Instruction Set
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5.1 Format 1: move shifted register
Figure 5-2: Format 1
5.1.1 Operation
These instructions move a shifted value between Lo registers. The THUMB assembler syntax is shown inòTable 5-2: Summary of format 1 instructions.
NoteAll instructions in this group set the CPSR condition codes.OP THUMB assembler ARM equivalent Action
00LSL Rd, Rs, #Offset5MOVS Rd, Rs, LSL #Offset5Shift Rs left by a 5-bit immediate value
and store the result in Rd.01 LSR Rd, Rs, #Offset5 MOVS Rd, Rs, LSR #Offset5 Perform logical shift right on Rs by a 5-
bit immediate value and store the result in Rd.10ASR Rd, Rs, #Offset5MOVS Rd, Rs, ASR #Offset5Perform arithmetic shift right on Rs by a
5-bit immediate value and store the
result in Rd.Table 5-2: Summary of format 1 instructions
0123456789101112131415
Offset5 Rs000
Destination register
Source register
Immediate value
Opcode
Op Rd0 - LSL1 - LSR2 - ASR
THUMB Instruction Set
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5.1.2 Instruction cycle times
All instructions in this format have an equivalent ARM instruction as shown inòTable5-2: Summary of format 1 instructions
on page 5-5. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. For more information on instruction cycle times, please refer toòChapter 10, Instruction CycleOperations
.5.1.3 ExamplesLSR R2, R5, #27 ; Logical shift right the contents ; of R5 by 27 and store the result in R2. ; Set condition codes on the result.THUMB Instruction Set
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5.2 Format 2: add/subtract
Figure 5-3: Format 2
5.2.1 Operation
These instructions allow the contents of a Lo register or a 3-bit immediate value to be added to or subtracted from a Lo register. The THUMB assembler syntax is shown inTable 5-3: Summary of format 2 instructions.
NoteAll instructions in this group set the CPSR condition codes.Op I THUMB assembler ARM equivalent Action
00ADD Rd, Rs, RnADDS Rd, Rs, RnAdd contents of Rn to contents of Rs. Place
result in Rd.0 1 ADD Rd, Rs, #Offset3 ADDS Rd, Rs, #Offset3 Add 3-bit immediate value to contents of
Rs. Place result in Rd.
10SUB Rd, Rs, RnSUBS Rd, Rs, RnSubtract contents of Rn from contents of
Rs. Place result in Rd.
1 1 SUB Rd, Rs, #Offset3 SUBS Rd, Rs, #Offset3 Subtract 3-bit immediate value from
contents of Rs. Place result in Rd.Table 5-3: Summary of format 2 instructions
0123456789101112131415
Rn/Offset3 Rs1000
Destination register
Opcode
Source register
0 - ADD
Register/
1 - SUB
Immediate value
Immediate flag
0 - Register operand
1 - Immediate operand
1IOp Rd
THUMB Instruction Set
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5.2.2 Instruction cycle times
All instructions in this format have an equivalent ARM instruction as shown inòTable5-3: Summary of format 2 instructions
on page 5-7. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. For more information on instruction cycle times, please refer toòChapter 10, Instruction CycleOperations
.5.2.3 ExamplesADD R0, R3, R4; R0 := R3 + R4 and set condition codes on ; the result. SUB R6, R2, #6 ; R6 := R2 - 6 and set condition codes.THUMB Instruction Set
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5.3 Format 3: move/compare/add/subtract immediate
Figure 5-4: Format 3
5.3.1 Operations
The instructions in this group perform operations between a Lo register and an 8-bit immediate value.The THUMB assembler syntax is shown inò
Table 5-4: Summary of format 3
instructions NoteAll instructions in this group set the CPSR condition codes.Op THUMB assembler ARM equivalent Action
00MOV Rd, #Offset8MOVS Rd, #Offset8Move 8-bit immediate value into Rd.
01 CMP Rd, #Offset8 CMP Rd, #Offset8 Compare contents of Rd with 8-bit
immediate value.10ADD Rd, #Offset8ADDS Rd, Rd, #Offset8Add 8-bit immediate value to contents of Rd
and place the result in Rd.11 SUB Rd, #Offset8 SUBS Rd, Rd, #Offset8 Subtract 8-bit immediate value from
contents of Rd and place the result in Rd.Table 5-4: Summary of format 3 instructions
0123456789101112131415
RdOp100Offset8
Source/destination register Immediate value
Opcode
0 - MOV1 - CMP2 - ADD3 SUB
THUMB Instruction Set
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5.3.2 Instruction cycle times
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