Design compiler keep hierarchy

What is structuring and flattening in VLSI?
Structuring is usually recommended for designs with regular structured logic.
Flattening tries to convert logic into two-level, Sum-of-Products representation.
Flattening produces fast logic (by minimizing the levels of logic between the inputs and outputs) at the expense of the area increase..
What is Synopsys design compiler used for?
Design Compiler Graphical provides optimization technologies that monotonically reduce gate-to-gate area by an average of 10% while maintaining timing Quality of Results (QoR).
These advanced optimizations operate on both new and legacy design netlists, with or without physical information and at all process nodes..
What is the ungrouping in VLSI design?
Ungrouping.
Ungrouping merges sub-designs of a given level of the hierarchy into the parent cell or design.
It removes hierarchical boundaries and allows Design Compiler to improve timing by reducing the levels of logic and to improve area by sharing logic..
The analyze and elaborate commands are two different commands, allowing designers to initially analyze the design for syntax errors and RTL translation before building the generic logic for the design.
The generic logic or GTECH components are part of the Synopsys generic technology independent library.

FPGA Compiler cannot move logic across levels of hierarchy. To maintain the hierarchy you need two CLBs to implement the TOP design. FPGA Compiler uses one

Using FPGA Compiler, you can optimize a design while preserving these hierarchical boundaries.

How to remove hierarchy in a design (netlist) & make it flat?

the ungroup command removes the hierarchy in the design (netlist) and make it flat. you can use set_flatten command (options are true and false) to enable and disable this behavior during logic optimization (during compile)..
By default it is set to be false..

Should a designer use a dynamic compiler?

Designers working on complex products can focus on engineering their applications, rather than tracking net and component connections across their schematics.
You won’t have to choose between these two design methodologies:

you only need to worry about keeping your schematics organized

and the dynamic compiler handles the rest.

Should I use hierarchical schematics?

In general, as your device becomes more complex and includes ,a large number of discrete components or uses high pin-count components (e.g., FPGAs), you should consider using hierarchical schematics.
The answer can also depend on how you’ve organized your design.

Should you use a flat hierarchy?

While this might work fine for simpler boards with a small number of connections, you’ll put yourself at risk of major design errors in more complex designs.
Flat hierarchies also lack the parent-child relationships required to run DRCs, simulations, and define connections throughout your design.

Design compiler keep hierarchy

What is structuring and flattening in VLSI?

What is Synopsys design compiler used for?

What is the ungrouping in VLSI design?

How to remove hierarchy in a design (netlist) & make it flat?

Should a designer use a dynamic compiler?

Should I use hierarchical schematics?

Should you use a flat hierarchy?