Jun 10, 2020Newbie level 31) Warning: ./ahb_slave_ram.2) Warning: ./ahb_slave_ram.3) Warning: In design 'ahb_slave', input pin 'STALL_pre' of hierarchical cell ' Synopsys design compiler error problem | Forum for ElectronicsDesign Compiler warnings | Forum for ElectronicsDesign compiler warning | Forum for Electronics[SOLVED] - Synopsys IC Compiler warning and ErrorMore results from www.edaboard.com
Jun 10, 2020Synopsys Design Compiler Warnings Hey I wrote some code in Verilog (it's an AHB slave design) and when I run it in Design Compiler I have the following Design Compiler warnings | Forum for ElectronicsDesign compiler warning | Forum for Electronics[SOLVED] - Synopsys IC Compiler warning and Error[question] a warning about design compiler | Forum for ElectronicsMore results from www.edaboard.com
Jun 10, 2020You can use man command to understand each warning such as: man VER-130 and then look at the RTL. Thanks.Design Compiler warnings | Forum for ElectronicsDesign compiler warning | Forum for Electronics[SOLVED] - Synopsys IC Compiler warning and Error[question] a warning about design compiler | Forum for ElectronicsMore results from www.edaboard.com
Jun 10, 2020You can use man command to understand each warning such as: man VER-130 and then look at the RTL. Thanks.Synopsys design compiler error problem | Forum for ElectronicsDesign Compiler warnings | Forum for ElectronicsDesign compiler warning | Forum for Electronics[SOLVED] - Synopsys IC Compiler warning and ErrorMore results from www.edaboard.com
This warning is issued to verify that these are desired connections on the submodule. Be aware that compile can remove logic in a design that is redundant. So, compile can produce designs that display this warning if it determines that multiple inputs on a submodule are driven by the same logical signal.