Design compiler report_timing path

What is clock path?
The path wherein clock traverses is known as clock path.
Clock path can have only clock inverters and clock buffers as its element.
Clock path may be passed trough a “gated element” to achieve additional advantages.
In this case, characteristics and definitions of the clock change accordingly..
What is launch path and capture path?
Launch path is launch clock path which is responsible for launching the data at launch flip flop.
And Similarly Capture path is also a part of clock path.
Capture path is capture clock path which is responsible for capturing the data at capture flip flop..
What is path group in timing analysis?
It involves dividing the paths in your design into different groups based on their characteristics, such as clock domain, logic depth, or criticality.
By doing so, you can optimize the timing constraints and analysis for each group, rather than applying the same settings to all paths..
What is the critical path in STA?
The critical path is defined as the path between an input and an output with the maximum delay.
Once the circuit timing has been computed by one of the techniques listed below, the critical path can easily be found by using a traceback method..
Half Cycle Path.
Timing path that is designed to take half clock cycle (both of the clock edges) for the data to propagate from the start point to the endpoint.
Start point and endpoint are flops clocked by the same clock.
The critical path is defined as the path between an input and an output with the maximum delay.
Once the circuit timing has been computed by one of the techniques listed below, the critical path can easily be found by using a traceback method.
The path wherein clock traverses is known as clock path.
Clock path can have only clock inverters and clock buffers as its element.
Clock path may be passed trough a “gated element” to achieve additional advantages.
In this case, characteristics and definitions of the clock change accordingly.
The set_output_delay command sets output path delays on output ports relative to a clock edge.
Output ports have no output delay unless you specify it.
For in/out (bidirectional) ports, you can specify the path delays for both input and output modes.

Report Timing: Found 2 hold paths (0 violated). Worst case slack is 0.289. Tcl Command: report_timing -append -hold -file timing.rpt -panel_name {Report Timing}

How many timing paths are there?

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I'm trying to get the timing report of STA.
As I know, basically, there are 4 types of timing paths.

Design compiler report_timing path

What is clock path?

What is launch path and capture path?

What is path group in timing analysis?

What is the critical path in STA?

How many timing paths are there?