Design compiler load_of

Feb 8, 2021I I think set_load affects to output path timing. because if a big load added to output path, then output_delay value also corresponding to it.Unconstrained PAth in a fulladder design - DC - Forum for Electronicsdesign compiler retiming questions | Forum for Electronics[SOLVED] - synthesis problem on Design Compiler - EDAboard.comwho can share a sample Design Complier synthesis script?More results from www.edaboard.com