[PDF] Assembly Language Instructions

20383_3Experiment_4.pdf

Experiment 4

Assembly Language Instructions

Lab Objective

In this lab, we will learn some basic ARM assembly language instructions and write a simple programs in assembly language.

ARM Assembly Instructions

ARM assembly instructions can be divided in three dierent sets. Data processinginstructions manipulate the data within the registers. These can be arith- metic (sum, subtraction, multiplication), logical (boolean operations), relational (comparison of two values) or move instructions. Memory accessinstructions move data to and from the main memory. Since all other opera- tions only work with immediate constant values (encoded in the instruction itself) or with values from the registers, the load/store instructions are necessary to deal with all but the smallest data sets. Branchinstructions instructions change the control ow, by modifying the value of the Program Counter (R15). They are needed to implement conditional statements, loops, and function calls.

Data processing Instructions

ARM data processing instructions enable the programmer to perform arithmetic and logical operations on data values in registers. All other instructions just move data around and control the sequence of program execution, so the data processing instructions are the only instructions which modify data values. Most data processing instructions can process one of their operands using the barrel shifter (discussed in class). If you use the `S' sux on a data processing instruction, it updates the ags in the CPSR. Move and logical operations update the carry ag C, negative ag N, and zero ag Z. The carry ag (C) is set as a result of the barrel shift when the last bit is shifted out. The negative ag (N) is set to bit 31 of the result. The zero ag (Z) is set if the result is zero. 41

42CHAPTER 4. ASSEMBLY LANGUAGE INSTRUCTIONS

Move Instruction (MOV)

Inside the processor, the data resides in the registers. MOV is the basic instruction that moves the constant data in the register or move that data from one register to another. In the Thumb instruction set MOVT, instruction moves 16-bit immediate value to top halfword (bits 16 to

31) and the bottom halfword remains unaltered.Example 4.1

MOV

R 0, # 0xFF

; M ove

8 b i th exn umbert oR 0MOVR 1, # 0x281; M ove1 2b i ts ignedh exn umbert oR 1MOVR 4, # 0x D364; M ove1 6b i th exn umbert ot hel ower;h alfwordo fR 4

MOVT

R 4, # 0xFFB1

; M ove

1 6b i th exn umbert ot heu pper;h alfwordo fR 4

MOV

R 5, R 4

; M ove t he c ontents o f R 4 t o R 5

Shift and Rotate instructions

Shift and Rotate instructions are used to change the position of bit values in a register. Dierent variants of these instructions are discussed in this manual.

Logical Shift Right (LSR)

This instruction is similar to the unsigned divide by 2 nwherenspecies the number of shifts. Execute the following instructions in your compiler and observe the results.Example 4.2 MOV

R 0, # 0x 06

; M ove 0 x06 t o R 0 MOV

R 3, # 0x 200

; M ove 0 x200 t o R 5 MOV

R 5, # 0x9B1D

; M ove 0 x9B1D t o R 5 STOP LSR

R 4, R 3, # 6

;

L og ical

s h i f t r i g h t b y 6 b i t s LSR

R 2, R 3, R 0

;

L og ical

s h i f t r i g h t b y t he v alue ; i n l ower b yte o f R 0 LSR

R 6, R 5, # 5

;

L og ical

s h i f t r i g h t b y 5 b i t s w i thou t ; f l a g s u pdate LSRS

R 7, R 5, # 5

;

L ogic al

s h i f t r i g h t b y 5 b i t s w ith ; f l a g s u pdate 43
B S TOP END ; E nd o f t he p rogram

Arithmetic Shift Right (ASR)

This instruction is similar to the signed divide by 2 nwherenspecies the number of shifts. Execute the following instructions in your compiler and observe the result.Example 4.3 MOV

R 0, # 0x 07

; M ove 0 x07 t o l ower b yte o f R 0 MOV

R 3, # 0x669; M ovet he1 2b i ts ignedh exn umbert oR 3MOVR 5, # 0x D634; M ovet he1 6b i ts ignedh exn umbert oR 5MOVTR 5, # 0xFFB1; M ovet he1 6b i ts ignedh exn umbert o;u pperh alfwordo fR 5

STOP ASR

R 4, R 3, # 5

;

A r i t h m e t i c

s h i f t r i g h t b y 5 b i t s ASR

R 2, R 3, R 0

;

A r i t h m e t i c

s h i f t r i g h t b y t he l ower ; b yte v alue o f R 0 ASR

R 6, R 5, # 5

;

A r i t h m e t i c

s h i f t r i g h t b y 5 b i t s ; w i thou t f l a g s u pdate ASRS

R 7, R 5, # 5

;

A r i t h m e t i c

s h i f t r i g h t b y 5 b i t s ; w ith f l a g s u pdate B S TOP END ; E nd o f t he p rogram

Logical Shift Left (LSL)

Logical shift left instruction works ne for both signed and unsigned numbers. This instruction is synonymous to multiply by 2 nwherenspecies the number of shifts.Example 4.4 MOV

R 7, # 0xC

; M ove 0 x0C t o l ower b yte o f R 7 MOV

R 0, # 0x281; M ovet he1 2b i ts ignedh exn umbert oR 0MOVR 2, # 0x 25C3; M ovet he1 6b i ts ignedh exv alue;t ot hel owerh alfwordo fR 2

MOV

R 4, # 0x 593C

; M ove t he

1 6b i th exv alue;t ot hel owerh alfwordo fR 4

MOVT

R 4, # 0x A377

; M ove t he

1 6b i th exv alue;t ot heu pperh alfwordo fR 4

44CHAPTER 4. ASSEMBLY LANGUAGE INSTRUCTIONSSTOP

LSL

R 1, R 0, # 3

;

L og ical

s h i f t l e f t b y 3 b i t s LSL

R 3, R 2, R 7

;

L og ical

s h i f t l e f t b y t he v alue ; i n t he l ower b yte o f R 7 LSL

R 5, R 4, # 10

;

L og ical

s h i f t l e f t b y 1 0 b i t s ; w i thou t f l a g s u pdate LSLS

R 6, R 4, # 10

;

L ogic al

s h i f t l e f t b y 1 0 b i t s ; w ith f l a g s u pdate B S TOP END ; E nd o f t he p rogram

Rotate Right (ROR)

Bit-rotates do not discard any bits from the register. Instead, the bit values are removed from one end of the register and inserted into the other end.Example 4.5 MOV

R 0, # 0x 9

; M ove 0 x09 t o l ower b yte o f R 0 MOV

R 1, # 0x 25C3

; M ove t he

1 6b i ts ignedh exv alue;t ot hel owerh alfwordo fR 2

MOV

R 3, # 0x 73A2

; M ove t he

1 6b i th exv alue;t ot hel owerh alwordo fR 3

MOVT

R 3, # 0x 5D81

; M ove t he

1 6b i th exv alue;t ot heu pperh alfwordo fR 3

STOP ROR

R 2, R 1, # 24

;

R otate

r i g h t l e f t b y 2 4 b i t s ROR

R 7, R 3, R 0

;

R otate

r i g h t b y t he v alue ; i n t he l ower b yte o f R 0 ROR

R 4, R 3, # 10

;

R otate

r i g h t b y 1 0 b i t s ; w i thou t f l a g s u pdate RORS

R 5, R 3, # 10

;

R otate

r i g h t b y 1 0 b i t s ; w ith f l a g s u pdate B S TOP END ; E nd o f t he p rogram

Rotate Right Extended (RRX)

RRX is a ROR operation with a crucial dierence. It rotates the number to the right by one place but the original bit 31 is lled by the value of the Carry ag and the original bit 0 is moved into the Carry ag. This allows a 33-bit rotation by using both the register and the 45
carry ag.Example 4.6 MOV

R 3, # 0x D129

; M ove t he

1 6b i th exv alue;t ot hel owerh alfwordo fR 3

MOVT

R 3, # 0x F29A

; M ove t he

1 6b i th exv alue;t ot heu pperh alfwordo fR 3

STOP RRX

R 4, R 3

;

R otate

r i g h t e xtended w it hout f l a g s u pdate RRXS

R 6, R 3

;

R otate

r i g h t e xtended w ith f l a g s u pdate B S TOP END ; E nd o f t he p rogram

Memory Access Instructions

ARM is a load/store architecture. It does not support memory to memory data processing operations. All data processing operations are executed in the registers .i.e., data values needed for an operation must be moved into registers before using them. We need instructions that interact with memory to move data from memory to registers and vice versa. ARM has three sets of instructions which interact with main memory. 1.

Single register data transfer (LDR/STR)

2.

Blo ckdata transfer (LDM/STM)

3.

Single Data Sw ap(SWP)

In this lab manual, we will discuss single register data transfer instructions and dierent ad- dressing modes that can be used to move the contents from memory to registers and vice versa.

Single Register Data Transfer

The basic data transfer instructions supported by ARM assembler can load and store dierent size of data from and to the memory respectively.Example 4.7 THUMB ;

M arks

t he

T HUMB

m ode o f o peration

46CHAPTER 4. ASSEMBLY LANGUAGE INSTRUCTIONS;DataV ariablesa red eclaredi nD ATAA REA;AREAM yData, D ATA, R EADWRITE

X

S PACE

2 ; 2 b ytes f o r v a r i a b l e X a re r eserved ; i n m emory a t 0 x 20000000 data

S PACE

2 ; 2 b ytes f o r v a r i a b l e d ata i s d eclared i n m emory

;Theu serc ode( p rogram) i s p lacedi nC ODEA REA;AREA| . t e x t | , C ODE,R EADONLY, A LIGN=2

ENTRY ;

E NTRY

m arks t he s t a r t i n g p o i n t ; o f t he c ode e xecution

EXPORT

_ _main __main ;Userc odes t a r t s f romt hen extl i n e ;MOVR 0, # 0x2D MOV

R 1, # 0x 40

LDR

R 2, = d ata

; L oad t he a ddress o f d ata v a r i a b l e i n R 2 ADD

R 0, R 0, R 1

STR

R 0, [ R 2]

;

S tore

t he c ontents o f R 0 a t a ddress l oaded i n R 2 ;

O bserve

m emory w indow a t a ddress s p e c i f i e d i n R 2 STOP B S TOP ;

I n f i n i t e

l oop t o S TOP ALIGN END ; E nd o f t he p rogram , m atched w ith

E NTRY

k eyword LDR instruction can also be used to load any constant in the registers. Any 32-bit numeric constant can be constructed in a single instruction. It is used to generate constants that are out of range of the MOV and MVN instructions.Example 4.8 THUMB ;

M arks

t he

T HUMB

m ode o f o peration ;DataV ariablesa red eclaredi nD ATAA REAAREAM yData, D ATA, R EADWRITE

Result

S PACE

4 ; 4 b ytes r eserved f o r v a r i a b l e

R esult

47

;Theu serc ode( p rogram) i s p lacedi nC ODEA REA;AREA| . t e x t | , C ODE,R EADONLY, A LIGN=2

ENTRY ;

E NTRY

m arks t he s t a r t i n g p o i n t o f ; t he c ode e xecution

EXPORT

_ _main __main

;Userc odes t a r t s f romt hen extl i n e ;LDRR 1, = 0x458C3; L oadst hev alue0 x458C3i nR 1

; w hich i s o ut o f r ange o f M OV i n s t r u c t i o n LDR

R 2, = 0x A8261

LDR

R 4, = R esult

; L oad t he a ddress o f v a r i a b l e ; r e s u l t i n R 4 MOV

R 0, # 0

MUL

R 3, R 1, R 2

LSRS

R 3, # 9

;

L ogi cal

s h i f t r i g h t w ith f l a g s u pdate STR

R 3, [ R 4]

;

S tore

t he c ontents o f R 3 t o m emory ; a ddress a lready l oaded i n R 4 STOP B S TOP END

These instructions provide the most

exible way to transfer single data items between an ARM register and memory. The data item may be a byte, a 16-bit half-word, a 32-bit word or a

64-bit double word. An optional modier should be added to access the appropriate data type.

Following table shows the data types available and their ranges.typeData TypeRange

32-bit word0 to 2

321 or231to 2311Bunsigned Byte0 to 2

81SBSigned Byte27to 271Hunsigned Halfword0 to 2

161SHSigned Halfword215to 2151DDouble word0 to 2

641 (two registers used)In the following example Byte data type is used

Example 4.9

THUMB ;

M arks

t he

T HUMB

m ode o f o peration ;DataV ariablesa red eclaredi nD ATAA REA;

48CHAPTER 4. ASSEMBLY LANGUAGE INSTRUCTIONSAREAM yData, D ATA, R EADWRITE

High D CB 0 ; 1 b yte r eserved f o r v a r i a b l e H igh Low D CB 0 ; 1 b yte r eserved f o r v a r i a b l e L ow

Result

D CB 0 ; 1 b yte r eserved f o r v a r i a b l e

R esult

Result1

D CD 0 ; 4 b ytes r eserved f o r v a r i a b l e

R esult1

;Theu serc ode( p rogram) i s p lacedi nC ODEA REA;AREA| . t e x t | , C ODE,R EADONLY, A LIGN=2

ENTRY ;

E NTRY

m arks t he s t a r t i n g p o i n t o f ; t he c ode e xecution

EXPORT

_ _main __main ;Userc odes t a r t s f romt hen extl i n e ;LDRR 0, = H igh; R 0= LDR

R 1, = Low

; R 1 = LDR

R 2, = R esult

; R 2 = LDR

R 5, = R esult1

; R 5 = MOV

R 3, # 0x 5

MOV

R 4, # 0x 8

LSL

R 3, # 4

;

S h i f t

t he l ower n i b b l e t o u pper n i b b l e o f ; t he l e a s t s i g n i f i c a n t b yte STRB

R 3, [ R 0]

;

O bserve

m emory w indow a t t he a ddress ; s tored i n R 0 STRB

R 4, [ R 1]

;

O bserve

m emory w indow a t t he a ddress ; s tored i n R 1 ORR

R 3, R 3, R 4

; S et l ower f our b i t s o f R 3 e qual t o ; l ower f our b i t s o f R 4 STRB

R 3, [ R 2]

;

O bserve

m emory w indow a t t he a ddress ; s tored i n R 2 STR

R 3, [ R 5]

;

T akes

3 2 b i t s t o s tore t he r e s u l t ALIGN STOP B S TOP END 49

Addressing Modes

The ARM instruction set provides dierent modes for addressing memory. These modes incor- porate one of the indexing methods: preindex with writeback, preindex, and postindex.Example 4.10 THUMB ;DataV ariablesa red eclaredi nD ATAA REA;AREAM yData, D ATA, R EADWRITE data

S PACE

4 ; 4 b ytes r eserved f o r v a r i a b l e d ata AREA | . t e x t | , C ODE ,

R EADONLY

,

A LIGN

=2 ENTRY ;

E NTRY

m arks t he s t a r t i n g p o i n t o f ; t he c ode e xecution

EXPORT

_ _main __main ;Userc odes t a r t s f romt hen extl i n e ;MOVR 0, # 0x 4A8 MOV

R 1, # 0x 761

MOV

R 4, # 0x8D

MOV

R 3, # 0x0C

SUB

R 1, R 1, R 0

;O f f s e tA ddressingLDRR 2, = d ata; L oadt hea ddresso fd atai nR 2 STR

R 1, [ R 2]

;

S tore

t he

3 2b i tc ontentso fR 1r e g i s t e r ;a tt hea ddressl oadedi nR 2. T hec ontents

; o f R 2 d oes n ot c hange . STR

R 1, [ R 2, # 4]

; A w ord i n r e g i s t e r R 1 i s s tored a t ; m emory a ddress c a l c u l a t e d b y a dding t he ; o f f s e t t o R 2 .

C ontents

o f R 2 d oes n ot c hange . STR

R 1, [ R 2, R 3]

;

S tore

t he c ontents o f R 1 a t m emory a ddress ; c a l c u l a t e d b y a dding v alue i n t he b ase ; r e g i s t e r R 2 t o t he v alue i n t he r e g i s t e r R 3 . ; B oth R 2 a nd R 3 r emain u nchanged .

50CHAPTER 4. ASSEMBLY LANGUAGE INSTRUCTIONSSTRR 1, [ R 2, R 3, L SL# 2]

;

S tore

t he

3 2b i tv aluei nR 1t ot hem emorya ddressc a l c u l a t e d b y;a ddingt hea ddressi nb aser e g i s t e r R 2t ot hev alueo btained

; b y s h i f t i n g t he c ontents o f R 3 t owards l e f t b y 2 b i t s . R 2 ; a nd R 3 r emain u nchanged . ;PostindexA ddressingLDRR 2, = d ata; L oadt hea ddresso fd atai nR 2 STR

R 1, [ R 2] , # 12

;

C ontents

o f R 1 w i l l b e s tored i n m emory a t t he a ddress l oaded i n ; R 2 . R 1 i s u pdated w ith n ew a ddress a f t e r a dding t he c onstant , ; s pecified , t o i t . STR

R 4, [ R 2] , # 24

;PreindexA ddressingLDRR 2, = d ata; L oadt hea ddresso fd atai nR 2 STR

R 1, [ R 2, # 32]!

;

3 2b i tw ordi nR 1w i l l b es toredi nm emorya ta na ddress;c a l c u l a t e d b ya dding3 2t ot hea ddressl oadedi nR 2.

; T he c ontents o f R 2 a lso g et u pdated w ith t h i s n ew a ddress STOP B S TOP END

Exercises

1. R1 = 0x37AF. Apply LSR instruction on this v alueand store the result in R2. Consider shift amounts as 1,3,12. 2. Assume R3 = 0x395A62. Apply ASR instruction and s torethe result in R4. Consider shift amounts as 1,5,15. 3. R3 register c ontainsa negativ ev alue-321. Apply the LSR and ASR instru ctionand observe the result. Which instruction gives the correct result and why. Write your result in both the cases and explain. 4. Supp oseR0 register con tainsan unsigned hex v alue0xA642. Multipl ythis hex v alueb y

8 and write the result in R2.

5. Register R1 has signed v alue-458 and register R2 has unsingned v alue458. Apply the LSL operation on both the registers and observe the result. (Hint: Hexadecimal representation of 458 is 0x1CA) 51
6. Compare the results of question 5 and explain wh yASL is not needed. 7. What is the net result if a bit pattern (32 bits) is logical left shifted 2 p ositionsand then logical right shifted 2 positions? 8. Assume that R0 register con tain0xC5AF2. Using shift op erationmo vethe con tentsof

R0 to R4.

9. No wc onsiderthe v alueof R0 in previous as a signed v alue(usesign extension) and m ultiply it by 8 and observe the result 10. Mo vehexadecimal v alue0xA964 to the register R1 an dobserv ethe result of eac hof LSR, ASR, LSL, ROR and RRX instructions. Assume the shift amount equal to 1. State your ndings. 11. Mo vethe hexadecimal v alue0xD29D1C8B to register R5 and apply the op erationsLSR,

ASR, LSL, ROR and RRX with

ags update. Write your results. 12. Rotate the con tentsof R3 register to left b y12 bits. Assume R3 = 0x568A1F C3. 13. Consider R5 = 0x65F F.Mo vethis v alueto the higher 16 bits using only one instruction. 14. Consider R6 = 0x76543210. Sw apthe top and b ottomhalv esof R6. 15. P erforma RRX op erationon R6 register and observ ethe result.