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Andreas Aal

1 , Gottfried Kurz 2 , André Clausner 3 1

Electronic Analysis / Robustness (EEIP/1), Volkswagen AG, Berliner-Ring 2, 38436 Wolfsburg, Germany 2

GLOBALFOUNDRIES Dresden Module One LLC & Co. KG, Wilschdorfer Landstrasse 101, 01109 Dresden, Germany

3

Fraunhofer Institute for Ceramic Technologies and Systems, Maria-Reiche-Strasse 2, 01109 Dresden, Germany

Phone: +49-(0)5361-9-38277; Fax: +49-(0)5361-9-57-38277; e-mail: andreas.aal@volkswagen.de Intermittent Functional Loss of Non-Degraded Advanced

Semiconductor Technology based Products

in Harsh Environments - Causes, Reproducibility, Mitigation 14 th International Conference

Reliability and Stress

-Related Phenomena in

Nanoelectronics

- Experiment and Simulation

Bad Schandau, Germany, May 30 - June 1, 2016

Content

Page 2

Background

1

Motivation

2

Experimental Approach

3 SRAM read disturb sensitivity under mechanical load 4 Primitive device electrical aging behavior under mechanical load 5

Discussion

6

Summary

7

Page 3

1. Background

Future Mobility: Zero Emission, intuitiv, online

The future is a 4wheel computer with client & server functionality - the ultimate mobile device

Page 4

1. Background

Semiconductor Technology - Enabler for Functions that matter Automotive needs leading-edge technologies from a functional perspective, but ...

Application CPU:

14/16 nm FinFET

(Samsung/TSMC)

Baseband CPU:

20 nm SOC

Power Amplifier Modul:

100 nm GaN

LTE-Modul:

28 nm CMOS

NAND Flash:

15 -20 nm MLC Key -Technologies (i.e. Smartphone) Automotive: New digital Products & Services

Big Data

Connected Car

Cloud- Computing

Autonomous

Driving

Page 5

2. Motivation

The challenge - AST* in automotive environments

This work: focuses on mech. induced parametric deviations ... ... function is bound to technology, but technology is bound to initial key-product design Reliability & performance of those technologies @ risk under automotive loads

Risks:

Stress exceeds strength

EOL reached too early (mission profile)

General mech. construction insufficience (cracks, delamination etc.)

Parametric deviations

Permanent w/o aging effect

Reversible / intermittent

Partially permanent / reversible with aging effect *AST = Advanced Semiconductor Technologies

Page 6

2. Motivation

The challenge - AST in automotive environments

Task: Mimic automotive loads and follow failure RCA* *RCA = Root Cause Analysis

Application

Awareness of technology sensitivity to thermo-

mechanical stress insufficient AEC-Q100 qualification in sockets insufficient to mimic board -level effects under real reflow conditions Wafer technology qualification did not sufficiently consider CPI / CPBI* Gaps

Similar effect observed

for 3 IC vendors / technologies in 2014 so not a single case * CPI / CPBI- chip package-board interaction Parametric drifts outside specified values after 1 st operation

Lucero, IRPS 2015

Leatherman, IRPS 2012

Page 7

3. Experimental Approach

Quantitative mech. loads & typ. environmental loads Quantify stress, watch effects - conclude knowledge based

Approach I

Analysis of SRAM read disturb sensitivity under mechanical load

Nano-indentation

VdipR - Tests

FEM Simulation of mechanical induced stress @ transistor level caused by external forces Calibration of simulation & electrical measurements

Approach II

Analysis of primitive device electrical aging behavior under mechanical load Effect of uHAST, TC, wafer thinning on HCI behavior

Page 8

4. Experimental - SRAM read disturb

Approach I - mechanical setup for n-indentation

Application of mech. stress by n-indentation @ chip back side

28 nm HKMG 64 Mbit SRAM, full process flow

Wafer thinning to 250 µm / Flipchip assembly to 948µPGA package

ATE test at 85°C / 25°C of assembled SRAMs

Remove of package lid and further down thinning of remaining Si- thickness (min. 35 Ɋm)

RD - Procedure (RDP)

Write step @ V

nom (checkerboard pattern)

Voltage dip down to VdipR

Read (disturb) step

Voltage rise to V

nom & read with pass/fail assessment

Repeat @ different mech. load conditions

Calibration I

VdipR chosen at threshold to bit flip (high sensitivity to mech. load) Drawback - background noise solution: statistical averaging by repeating RDP (fail assessment when > 10 fails in 20 repetitions or # fails per 50

VdipR repetitions )

Page 9

4. Experimental - SRAM read disturb

Approach I - VdipR Test

Fail calibration to mech. load

Page 12

4. Results

- SRAM read disturb Approach I - Simulation of mechanical induced stress @ transistor level caused by external forces

Image overlay of

VdipR and von-Mises stress simulation @ 1.3 N

Page 13

4. Results

- SRAM read disturb Approach I - Simulation of mechanical induced stress @ transistor level caused by external forces

Image overlay of

VdipR and hydrostatic stress simulation @ 1.3 N

Page 14

4. Results

- SRAM read disturb Approach I - Simulation of mechanical induced stress @ transistor level caused by external forces

Image overlay of

VdipR and normal stress in x direction simulation @ 1.3 N

Page 15

4. Results

- SRAM read disturb Approach I - Simulation of mechanical induced stress @ transistor level caused by external forces

Image overlay of

VdipR and normal stress in y direction simulation @ 1.3 N

Page 16

4. Results

- SRAM read disturb Approach I - Simulation of mechanical induced stress @ transistor level caused by external forces

Image overlay of

VdipR and normal stress in z (indentation) direction simulation @ 1.3 N

Page 17

4. Results

- SRAM read disturb Approach I - Calibration of simulation & electrical measurements Correlation of the SRAM functionality & simulation stresses through chip operation voltage shift with/without indenter load Determination of voltage shift required to hold cell stable (increase under indentation load) Shift in minimum required SRAM operation voltage with simulation stresses reliability criteria can be derived

Page 20

5. Results

- TQV test structure chip

Approach II - pure HCI aging, higher stress

HCI effect per channel length with distinct L - separation

Watch these curves on the next slide

Page 21

5. Results

- TQV test structure chip Approach II - HCI aging after uHAST, higher stress

TC/uHAST cause a ~const. shift of pMOS I

d,sat degradation

This form of graphical illustration is

insufficient to show the important things

These curves have shifted upwards

Page 22

5. Results

- TQV test structure chip

Approach II - pure HCI aging

Effect of HCI stress on pMOS I

d,sat degradation

Page 23

5. Results

- TQV test structure chip

Approach II - HCI aging after uHAST / TC + uHAST

Partially reversible shifts and variance increase

Page 24

5. Results

- TQV test structure chip

Approach II - HCI aging after uHAST / TC + uHAST

Shift & variation are voltage dependent

Page 25

5. Results

- TQV test structure chip Approach II - HCI aging & uHAST, TC, wafer thinning

Secondary stress effect is L and V dependent

Page 26

6. Discussion

Approach II

Usually package form-factor related tests are applied after tech-qual rather than investigating the effect already during technology qualification This approach then considers mechanical effects as linear, reversible and without effect on aging In addition the meaning of variability increase / decrease my be underestimated TC after wafer processing before wafer thinning & further assembly may reduce variability

Results from Intel (IRPS 2012) show that nMOS

I dsat shift is stronger affected as pMOS - we see pMOS sufficiently enough affected Shift is 37-50 % higher when going down from 25 °C to -10 °C Shift is 20 % higher when die thickness is reduced from 200 um to 120 um

Page 27

7. Summary

Approach I

Based on the combination of a smart n-indentation setup, optimized SRAM sensitivity, FEM simulations and corresponding calibration via cell operation voltage adjustment, ...

... it is now possible to quantify the transfer ratio of externally applied stress to local stress on Si device level, which ...

... can positively extend current DfR methodologies

Approach II

For the 1

st time the effect of mechanical-stress related tests on primitive device aging has been investigated The results & literature shows, how to further improve corresponding test scenarios ( test @ lower temp, decrease die thickness etc.) The effect of mechanical-stress has the potential to significantly change primitive device aging and therefore modelling

Page 28

ACKNOWLEDGEMENTS

Christoph Sander - IKTS

Martin Gall

- IKTS

Ardechir

Pakfar - GLOBALFOUNDRIES

Michael Otto

- GLOBALFOUNDRIES

Sebastian Dej

- GLOBALFOUNDRIES The authors thank the team from GLOBALFOUNDRIES and

Fraunhofer

IKTS for their support.

Especially to mention are:

5

Seite 29

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