[PDF] Multi-view design for cyber-physical systems

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Component 3

Component 2

View B

Component 1

View A

AssumptionGuarantee

A1? G2? P1?

Property 2

Property 1

A1G1 satisfied?

Component x

How to verify?

Integrate?

G2A2

Horizontal (Views)

Vertical (Refinement levels)

properties IURPWKHView Aproperties LQWKHView B m1m2 m2 m1 m1

Upper-monitorsDataStateDataStateDataStateDataStateOperation management platformSupply managementMachine states supervisionData AnalysisProduction managementHuman in loop decisionsHuman-Machine Interface

Behaviour viewControl viewHybrid viewPhysical viewProduct System Brake controller Speed Brake

Mechanism

Automatic train operation Brake sysSpeed Sensor

Security Implementation

SW design

Risk analysis

Attack tree

The Objective of

Security

Requires

Security configuration

(strategies)

Target

RAM

Simulation,FormalVerfication,

Testing

F1 F2 AES

Sec Conf

Function

Authentificaiton

Confidential

privacy key-based biometric-based ID Uses

Implement

Goal Means

Iteration V1

V2 Vn

HW design

System Design

Architecture

Application

Partitioning

Requirements of CPSsModelingUMLSysMLAADL

SysML-

Sec MARTE O

Correction

Model TransformationM2MM2TVerificationCode GenerationSimulation

Validation

Meta Meta-

Model Model

Meta-Model

InstanceOf

Model M1 M2 M3 M0 conform to MOF MM1 MM2 M2M MMs M1 M1+M2

Instance of

Modeling World

Real World

represented by M2

Inputgeneration

Rules

Graph of model A

Graph of rule model B

Result model C

Rule model

Source elements

Target elements

TRL (Transformation Rule Library)

OperatorsElements

TRE TRE

TRE (Transformation Rule

Expression)

Patterns

Specification

Parsed by

Realise

Tool

Specification

1..*

Pattern

Transformation

Rule Expression

Transformation

Rule Library

Operator

1..2

Element

(meta) Model

Attribute

1..* 1..* 1..* 1..* 1..*

Symbol

1..* 1..* patterns TREs TRLs (meta) models 1..* (meta) models elements 1..* attributes attributes elements operators

1..2elements

1..* 1..* operators TRLs symbols

Γ(source,target)

Γ< parent > source→target;

Port{Direction}:{Type}:{Secure}

Port P ort{Direction[in|out]}

Port@[ModelA,Security]

Port A B a,b,c?A Rax a,x)? RR(a,x)aRx

R(a,x)

ax ax

R(a,x) =?Γ(a,x)

E(a,x) a

x

E(a,x) =? R(a,x) =?Γ(a,x)

X={x,y,z}

¬R(a,X) =? ?x?X,¬R(a,x)

¬E(a,X) =? ?x?X,¬E(a,x)

a→x ax

Γa→x{t}+

ax t

Portfun

Port comm

¬ ¬aa

B aB

Γ¬Port{ordering} →Port;

Γ¬Port{ordering};

Port Port

Port@[ModelA,Security]

Port Port

Port Port

Exfun connection

ΓFunction

Γ¬Port

ΓExfun

ΓExfun

XML data

(model, TRE)

Adaptor

Json data

XML data

(xsd,xml) xml data

Import

Transformation Rule

LIB

Import

Arcadia Models

Functional

Design/Analysis

M2 M1

Temporary AADL Models

Architectural + Timing

Design/Analysis

Simulation

schedule 1 schedule 2

SimulateTraceback1234

conform tocorrespondingcorrespondingLegendconform toExportcorrespondingto be implementedconform toMetamodels of AADLMetamodels of ARCADIATemporary combinational Metamodelconform to

LC=< Comp,Fun,Port,Exfun,Mcf>

C omp=? iFiun F unPort

Exfun?

P ort×Port Mcf F un→Comp Comp

Fun Comp Mcf

Mcf F un→Comp

Port Port

Exfun

SC=< Type,Port,Connection,Annex >

Type Port

Connection

Annex

HA=< Ass,Ivar,V arhd,Conshd,Proc,ChP,Itr,Bitr>

Ass Ivar

V arhd

Conshd

Proc ChP Itr

Bitr:Itr→Proc

ΓComp system|process|

ΓFun abstract|thread||||

Comp |||

Fun ||||

Port|| ||

Exfun∅

∅||| Node ||

PP∅¬PP||

PL

EP=< EC,BA,Conn>

EC BA

Conn?EC×EC

PC=< Node,PP,PL >

Node PP PL Node

PL PP

ΓNode Device|Process|Memory|Bus

ΓPP->¬

ΓPL->|

{AllowedConnnectionType}+ :{AllowedMessageSize}+ {AllowedPhysicalAccess}+ :{TransmissionTime}+

B=< SFC,EP,B >

SFC EP B allocate allocate < C logi,CPhy> Port

Traction Control UnitAlarmTractional coe!cient

GeoMaps

GPS valueSetting valueMapsPosition

HMI

Locomotive

OperationDisplay

GPSBaliseSensor

20ms30msVoterVoterAcc/Dec valuestatussyncmsgcoe!cientRestriction

Restricted

condition

c_mrinc_princ_routstatusc_cvc_svc_rvcalculating speed valueCalculating Acc/DecSynchronizersyncc_ccc_sccc_csExpected speedc_secc_csCurrent speed60msAcc/Dec value40ms

θ=1

b ln(r

SysML-Sec (TTool)

Formal

Proof

CryptoLib

Simulator

SysML

Activity

Sequence

State Machine

BDD

Package

IBD

Parametric

UseCase

SysML-Sec (TTool)

Capella

SysML

Capella

Operational

Analysis

Logical

Architecture

Physical

Architecture

M1 M2

Meta-Model A'

Model a1:A

Model a1': A'

conform to 1 23
4 5 conform to

Source models

Resulting model

Language ALanguage B

conform to conform to

Meta-Model A

Arcadia

Meta-Model B

TTool subset of post-processing by

Functional PartSecurity/Safety Part

TRL import from

Meta-model

SysML

Meta-model

SysML-Sec

"stereotype»

Function

"stereotype»

Functional

Exchange

has has "stereotype»

Connection

"stereotype»

One-to-One

is_a "stereotype» port has 2x channeleventrequest is_ais_a is_a

Destination

Origin

"stereotype»

PrimitiveComp

hashas source target has "stereotype» bool:confidentiality bool:authenticity has "stereotype»

Functional

Input port

"stereotype»

Functional

Output port

has has

Component

equivalence

Extended

capability M1 M2

Meta-Model PhaseModel PhaseVerification Phase

Capella (Functional Design)

TTool (SysML-Sec)

Meta-Model A'

conform to

Meta-Model A

Arcadia

Meta-Model B

TTool TRL conform to

TTool (SysML-Sec) for safety verification

Setting security properties

Activities design

Reachability/Liveness

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