The 8086 Microprocessor PDF 194 Understanding 8085/8086 Microprocessors

ADVANCED MICROPROCESSORS & PERIPHERALS

Chapter 5: Basic Peripherals and their Interfacing with 8086/88 This book is intended as a textbook on 'Advanced Microprocessors' which is a compulsory ...

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The opcode available on the data bus is read by the processor and moved to the instruction register. ii. The RD signal is deactivated by making it logic 1. T4

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The 8086 Microprocessor

194 Understanding 8085/8086 Microprocessors and Peripheral ICs through requesting it (BIU) to perform read or write cycle to memory or I/O devices.

The 8086 Microprocessor

1. Draw the pin diagram of 8086.

Ans. There would be two pin diagramsone for MIN mode and the other for MA

X mode of

8086, shown in Figs. 11.1 and 11.2 respectively. The pins that differ wi

th each other in the two modes are from pin-24 to pin-31 (total 8 pins).

GND 1 40 V

AD -AD

0 15

2-16 & 39 35-38 A/S -A/S

16 3 19 6

NMI 17 34 BHE/S

INTR 18 33 MN/MX

CLK

19 32 RD

GND

20 INTEL

8086 31 HOLD

RESET

21 30 HLDA

READY

22 29 WR

TEST

23 28 M/IO

INTA

24 27 DT/R

ALE

25 26 DEN

Fig. 11.1: Signals of intel 8086 for minimum mode of operation

2. What is the technology used in 8086 µµµµµP?

Ans. It is manufactured using high performance metal-oxide semiconductor (HM OS) technology. It has approximately 29,000 transistors and housed in a 40-p in DIP package.

3. Mention and explain the modes in which 8086 can operate.

Ans. 8086 µP can operate in two modesMIN mode and MAX mode. When MN/MX pin is high, it operates in MIN mode and when low, 8086 operates in MAX mode.

194 Understanding 8085/8086 Microprocessors and Peripheral ICs through Quest

ions and Answers For a small system in which only one 8086 microprocessor is employed as a CPU, the system operates in MIN mode (Uniprocessor). While if more than one

8086 operate

in a system then it is said to operate in MAX mode (Multiprocessor).

GND 1 40 V

AD -AD

0 15

2-16 & 39 35-38 A/S -A/S

16 3 19 6

NMI 17 34 BHE/S

INTR 18 33 MN/MX

CLK

19 32 RD

GND

20 INTEL

8086 31 RQ/GT

RESET 21 30 RQ/GT

READY 22 29 LOCK

TEST

23 28 S

2 QS 1

24 27 S

1 QS

0 25 26 S0

Fig. 11.2: Signals of intel 8086 for maximum mode of operation The bus controller IC (8288) generates the control signals in case of

MAX mode, while

in MIN mode CPU issues the control signals required by memory and I/O de vices.

4. Distinguish between the lower sixteen address lines from the upper four.�

Ans. Both the lower sixteen address lines

(AD

ŠAD ) and the upper four address lines

0 15 (A /S Š A /S ) are multiplexed. 16 3 19 6

During T

1 , the lower sixteen lines carry address (A 0

Š A

15 , while during T 2 , T 3 and T 4 they carry data.

Similarly during T

1 , the upper four lines carry address (A 16 - A 19 ), while during T 2 T 3 and T 4 , they carry status signals. 5. In how many modes the minimum-mode signal can be divided? Ans. In the MIN mode, the signals can be divided into the following basic gro ups: address/data bus, status, control, interrupt and DMA. 6.

Tabulate the common signals, Minimum mode signals and Maximum mode signals. Also mention their functions and types.

Ans. Table 11.1 shows the common signals, Minimum mode signals and the Maximu m mode signals, along with the functions of each and their types.

The 8086 Microprocessor 195

Table 11.1 : (a) Signals common to both minimum and maximum mode, (b) Unique min imum-mode signals, (c) Unique maximum-mode signals for 8086.

Common signals

Name Function Type

AD15-AD0

A19/S6-A16/S3

MN/ MX READY RESET NMI INTR CLK V cc

GND Address/data bus

Address/status

Minimum/maximum Mode control

Read control

Wait on test cont

rol

Wait state control

System reset

Nonmasakable Interrupt request

Interrupt request

System clock

+5V

Ground Bidirectional, 3-state

Output, 3-state

Input

Output, 3-state

Input Input Input Input Input Input Input (a)

Minimum mode signals (MN/

=V cc

Name Function Type

HOLD HLDA M/ DT/ ALE

Hold request Hold acknowledge

Write control

IO/memory control

Data transmit/receive

Data enable

Address latch enable

Interrupt acknowledge Input

Output

Output, 3-state

Output

(b)

Maximum mode signals (MN/ �� =GND)

Name Function Type

QS1, QS0 Request/grant bus

access control

Bus priority lock control

Bus cycle status

Instruction queue status Bidirectional

Output, 3-state

Output

(c)

196 Understanding 8085/8086 Microprocessors and Peripheral ICs through Quest

ions and Answers 7. Mention the different varieties of 8086 and their corresponding speeds. Ans. The following shows the different varieties of 8086 available and their corresponding speeds.

Types Speeds

8086 5 MHz

8086-1 10 MHz

8086-2 8 MHz

8. Mention (a) the address capability of 8086 and (b) how many I/O line s can be accessed by 8086.

Ans. 8086 addresses via its A

0 -A 19 address lines. Hence it can address 2 20 = 1MB memory.

Address lines A

0 to A 15 are used for accessing I/O's. Thus, 8086 can access 2 16 = 64

KB of I/O's.

9. What is meant by microarchitecture of 8086?

Ans. The individual building blocks of 8086 that, as a whole, implement the s oftware and hardware architecture of 8086. Because of incorporation of additional fe atures being necessitated by higher performance, the microarchitecture of 8086 or for that matter any microprocessor family, evolves over time. 10. Draw and discuss the architecture of 8086. Mention the jobs performed by

BIU and EU.

Ans. The architecture of 8086 is shown below in Fig. 11.3. It has got two sep arate functional unitsBus Interface Unit (BIU) and Execution Unit (EU).

8086 architecture employs parallel processingi.e., both the units (

BIU and EU) work

at the same time. This is Unlike 8085 in which Sequential fetch and execute operations take place. Thus in case of 8086, efficient use of system bus takes plac e and higher performance (because of reduced instruction time) is ensured. zBIU has segment registers, instruction pointer, address generation and b us control logic block, instruction queue while the EU has general purpose registers, ALU, control unit, instruction register, flag (or status) register.

The main jobs performed by BIU are:

zBIU is the 8086"s interface to the outside world, i.e., all External bus operations are done by BIU. zIt does the job of instruction fetching, reading/writing of data/operand s for memory and also the inputting/outputting of data for peripheral devices. zIt does the job of filling the instruction queue. zDoes the job of address generation. The main jobs performed by the execution unit are: zDecoding/execution of instructions. zIt accepts instructions from the output end of instruction queue (resid ing in BIU) and data from the general purpose registers or memory.

zIt generates operand addresses when necessary, hands them over to BIU requesting it (BIU) to perform read or write cycle to memory or I/O de

vices. zEU tests the status of flags in the control register and updates them wh en executing instructions. zEU waits for instructions from the instruction queue, when it is empty. zEU has no connection to the system buses. CS ES SS DS

Instruction pointer

The 8086 Microprocessor 197

Address bus Data bus System buses

General Instructionregisters queue

Segment

registers

Address generation

and bus control 6 5 4 3 2 1 AH AL BH BL CH CL DH DL BP DI SI SP

Internal data bus

Arithmetic

logic unit Flags

Bus interface unit Execution unit

(BIU) (EU)

Fig. 11.3:

CPU model for the 8086 microprocessor. A separate execution unit (EU) and bus interface unit (BIU) are provided.

11. Explain the operations of instructions queue residing in BIU.

Ans. The instruction queue is 6-bytes in length, operates on FIFO basis, and receives the instruction codes from memory. BIU fetches the instructions meant for th e queue ahead of time from memory. In case of JUMP and CALL instructions, the queue is dumped and newly formed from the new address.

198 Understanding 8085/8086 Microprocessors and Peripheral ICs through Quest

ions and Answers Because of the instruction queue, there is an overlap between the instru ction execution and instruction fetching. This feature of fetching the next in struction when the current instruction is being executed, is called Pipelining.

Time required for execution of

two instructions because of pipelining

Time required for execution of two

instructions without pipelining Time Saved F 1 D 1 E 1 F 2 D 2 E 2 F 1 F 2 F 3 D 1 E 1 D 2 E 2 D 3 E 3 BIU EU

Overlapping

phases here,

F = Fetch

D= Decode

E= Execute

Fig.11.4: Pipelining procedure saves time

Fig. 11.4, which is self-explanatory, shows that there is definitely a t ime saved in case of overlapping phases (as in the case of 8086) compared to sequential phases (as in the case of 8085). Initially, the queue is empty and CS : IP is loaded with the required address (from which the execution is to be started). Microprocessor 8086 starts opera tion by fetching

1 (or 2) byte(s) of instruction code(s) if CS : IP address is odd (even).

The 1st byte is always an opcode, which when decoded, one byte in the qu eue becomes empty and the queue is updated. The filling in operation of the queue is not started until two bytes of the instruction queue is empty. The instructi on execution cycle is never broken for fetch operation. After decoding of the 1st byte, the decoder circuit gets to know whether the instruction is of single or double opcode byte. For a single opcode byte, the next bytes are treated as data bytes depen ding upon the decoded instruction length, otherwise the next byte is treated as th e second byte of the instruction opcode.

The 8086 Microprocessor 199

Execute it with data

bytes decoded by decoder Yes

Is it single

byte? From Memory

Decode first byte to

decide opcode lengths and update queue No

Take second byte from

queue as opcode. Decode second byte

Execute it with data bytes

as decoded by decoder Repeat the same procedure for successive contents of queue data

Update

opcode queue

Fig.11.5 :

The queue operation

For a 2-byte instruction code, the decoding process takes place taking b oth the bytes into consideration which then decides on the decoded instruction length and the numberquotesdbs_dbs11.pdfusesText_17

[PDF] The 8086 Microprocessor 194 Understanding 8085/8086 Microprocessors

The 8086 Microprocessor

1. Draw the pin diagram of 8086.

X mode of

8086, shown in Figs. 11.1 and 11.2 respectively. The pins that differ wi

GND 1 40 V

AD -AD

2-16 & 39 35-38 A/S -A/S

16 3 19 6

NMI 17 34 BHE/S

INTR 18 33 MN/MX

19 32 RD

20 INTEL

8086 31 HOLD

21 30 HLDA

22 29 WR

23 28 M/IO

24 27 DT/R

25 26 DEN

2. What is the technology used in 8086 µµµµµP?

3. Mention and explain the modes in which 8086 can operate.

194 Understanding 8085/8086 Microprocessors and Peripheral ICs through Quest

8086 operate

GND 1 40 V

AD -AD

2-16 & 39 35-38 A/S -A/S

16 3 19 6

NMI 17 34 BHE/S

INTR 18 33 MN/MX

19 32 RD

20 INTEL

8086 31 RQ/GT

RESET 21 30 RQ/GT

READY 22 29 LOCK

23 28 S

24 27 S

0 25 26 S0

MAX mode, while

4. Distinguish between the lower sixteen address lines from the upper four.�

Ans. Both the lower sixteen address lines

ŠAD ) and the upper four address lines

During T

Š A

Similarly during T

The 8086 Microprocessor 195

Common signals

Name Function Type

AD15-AD0

A19/S6-A16/S3

GND Address/data bus

Address/status

Minimum/maximum Mode control

Read control

Wait on test cont

Wait state control

System reset

Nonmasakable Interrupt request

Interrupt request

System clock

Ground Bidirectional, 3-state

Output, 3-state

Output, 3-state

Minimum mode signals (MN/

Name Function Type

Hold request Hold acknowledge

Write control

IO/memory control

Data transmit/receive

Data enable

Address latch enable

Interrupt acknowledge Input

Output

Output, 3-state

Output, 3-state

Output, 3-state

Output, 3-state

Output

Output

Maximum mode signals (MN/ �� =GND)

Name Function Type

8086 architecture employs parallel processingi.e., both the units (