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Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved.

ARM DDI 0406B

ARM

Architecture

Reference Manual

ARM v7-A and ARM v7-R edition iiCopyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved.ARM DDI 0406B

ARM Architecture Reference Manual

ARMv7-A and ARMv7-R edition

Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved.

Release Information

The following changes have been made to this document.

From ARMv7, the ARM

architecture defines different architectural profiles and this edition of this manual describes

only the A and R profiles. For details of the documentation of the ARMv7-M profile see Further reading on page xx.

Before ARMv7 there was only a single ARM Architecture Reference Manual, with document number DDI 0100. The first

issue of this was in February 1996, and the final issue, Issue I, was in July 2005. For more information see Further reading

on page xx.

Proprietary Notice

Words and logos marked with

or are registered trademarks or trademarks of ARM Limited in the EU and other

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the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted

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The product described in this document is subject to continuous developments and improvements. All particulars of the

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1. Subject to the provisions set out below, ARM hereby grants to you a perpetual, non-exclusive, nontransferable, royalty

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Change History

Date Issue Confidentiality Change

05 April 2007 A Non-Confidential New edition for ARMv7-A and ARMv7-R architecture profiles.

Document number changed from ARM DDI 0100 to ARM DDI 0406 and contents restructured.

29 April 2008 B Non-Confidential Addition of the VFP Half-precision and Multiprocessing Extensions, and many clarifications

and enhancements. ARM DDI 0406BCopyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved.iii

in whole or in part this ARM Architecture Reference Manual to third parties, other than to your subcontractors for the

purposes of having developed products in accordance with the licence grant in Clause 1 without the express written

permission of ARM; or (iv) translate or have translated this ARM Architecture Reference Manual into any other

languages.

3. THE ARM ARCHITECTURE REFERENCE MANUAL IS PROVIDED "AS IS" WITH NO WARRANTIES

EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF SATISFACTORY QUALITY, NONINFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE.

4. No licence, express, implied or otherwise, is granted to LICENSEE, under the provisions of Clause 1, to use the ARM

tradename, in connection with the use of the ARM Architecture Reference Manual or any products based thereon.

Nothing in Clause 1 shall be construed as authority for you to make any representations on behalf of ARM in respect of

the ARM Architecture Reference Manual or any products based thereon.

Where the term ARM is used to refer to the company it means "ARM or any of its subsidiaries as appropriate".

Note

The term ARM is also used to refer to versions of the ARM architecture, for example ARMv6 refers to version 6 of the

ARM architecture. The context makes it clear when the term is used in this way. Copyright © 1996-1998, 2000, 2004-2008 ARM Limited

110 Fulbourn Road Cambridge, England CB1 9NJ

Restricted Rights Legend: Use, duplication or disclosure by the United States Government is subject to the restrictions

set forth in DFARS 252.227-7013 (c)(1)(ii) and FAR 52.227-19.

This document is Non-Confidential. The right to use, copy and disclose this document is subject to the licence set out

above. ivCopyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved.ARM DDI 0406B ARM DDI 0406BCopyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved.v

Contents

ARM Architecture Reference Manual

ARMv7-A and ARMv7-R edition

Preface

About this manual ............................................................................... xiv

Using this manual ................................................................................ xv

Conventions ....................................................................................... xviii

Further reading .................................................................................... xx

Feedback ............................................................................................ xxi

Part A Application Level Architecture

Chapter A1 Introduction to the ARM Architecture

A1.1 About the ARM architecture ............................................................. A1-2 A1.2 The ARM and Thumb instruction sets .............................................. A1-3 A1.3 Architecture versions, profiles, and variants .................................... A1-4

A1.4 Architecture extensions .................................................................... A1-6

A1.5 The ARM memory model ................................................................. A1-7

A1.6 Debug .............................................................................................. A1-8

Chapter A2 Application Level Programmers' Model

A2.1 About the Application level programmers' model ............................. A2-2

Contents

viCopyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved.ARM DDI 0406B A2.2 ARM core data types and arithmetic ................................................ A2-3

A2.3 ARM core registers ........................................................................ A2-11

A2.4 The Application Program Status Register (APSR) ......................... A2-14

A2.5 Execution state registers ................................................................ A2-15

A2.6 Advanced SIMD and VFP extensions ............................................ A2-20 A2.7 Floating-point data types and arithmetic ........................................ A2-32 A2.8 Polynomial arithmetic over {0,1} .................................................... A2-67

A2.9 Coprocessor support ...................................................................... A2-68

A2.10 Execution environment support ..................................................... A2-69 A2.11 Exceptions, debug events and checks ........................................... A2-81

Chapter A3 Application Level Memory Model

A3.1 Address space ................................................................................. A3-2

A3.2 Alignment support ............................................................................ A3-4

A3.3 Endian support ................................................................................. A3-7

A3.4 Synchronization and semaphores .................................................. A3-12 A3.5 Memory types and attributes and the memory order model .......... A3-24

A3.6 Access rights .................................................................................. A3-38

A3.7 Virtual and physical addressing ..................................................... A3-40 A3.8 Memory access order .................................................................... A3-41 A3.9 Caches and memory hierarchy ...................................................... A3-51

Chapter A4 The Instruction Sets

A4.1 About the instruction sets ................................................................. A4-2

A4.2 Unified Assembler Language ........................................................... A4-4

A4.3 Branch instructions .......................................................................... A4-7

A4.4 Data-processing instructions ............................................................ A4-8 A4.5 Status register access instructions ................................................ A4-18

A4.6 Load/store instructions ................................................................... A4-19

A4.7 Load/store multiple instructions ..................................................... A4-22 A4.8 Miscellaneous instructions ............................................................. A4-23 A4.9 Exception-generating and exception-handling instructions ............ A4-24

A4.10 Coprocessor instructions ............................................................... A4-25

A4.11 Advanced SIMD and VFP load/store instructions .......................... A4-26 A4.12 Advanced SIMD and VFP register transfer instructions ................. A4-29 A4.13 Advanced SIMD data-processing operations ................................. A4-30 A4.14 VFP data-processing instructions .................................................. A4-38

Chapter A5 ARM Instruction Set Encoding

A5.1 ARM instruction set encoding .......................................................... A5-2 A5.2 Data-processing and miscellaneous instructions ............................. A5-4 A5.3 Load/store word and unsigned byte ............................................... A5-19

A5.4 Media instructions .......................................................................... A5-21

A5.5 Branch, branch with link, and block data transfer .......................... A5-27 A5.6 Supervisor Call, and coprocessor instructions ............................... A5-28 A5.7 Unconditional instructions .............................................................. A5-30

Contents

ARM DDI 0406BCopyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved.vii

Chapter A6 Thumb Instruction Set Encoding

A6.1 Thumb instruction set encoding ....................................................... A6-2 A6.2 16-bit Thumb instruction encoding ................................................... A6-6 A6.3 32-bit Thumb instruction encoding ................................................. A6-14 Chapter A7 Advanced SIMD and VFP Instruction Encoding

A7.1 Overview .......................................................................................... A7-2

A7.2 Advanced SIMD and VFP instruction syntax ................................... A7-3

A7.3 Register encoding ............................................................................ A7-8

A7.4 Advanced SIMD data-processing instructions ............................... A7-10 A7.5 VFP data-processing instructions .................................................. A7-24 A7.6 Extension register load/store instructions ...................................... A7-26 A7.7 Advanced SIMD element or structure load/store instructions ........ A7-27 A7.8 8, 16, and 32-bit transfer between ARM core and extension registers ..... A7-31 A7.9 64-bit transfers between ARM core and extension registers ......... A7-32

Chapter A8 Instruction Details

A8.1 Format of instruction descriptions .................................................... A8-2 A8.2 Standard assembler syntax fields .................................................... A8-7

A8.3 Conditional execution ....................................................................... A8-8

A8.4 Shifts applied to a register ............................................................. A8-10

A8.5 Memory accesses .......................................................................... A8-13

A8.6 Alphabetical list of instructions ....................................................... A8-14

Chapter A9 ThumbEE

A9.1 The ThumbEE instruction set ........................................................... A9-2 A9.2 ThumbEE instruction set encoding .................................................. A9-6 A9.3 Additional instructions in Thumb and ThumbEE instruction sets ..... A9-7 A9.4 ThumbEE instructions with modified behavior ................................. A9-8 A9.5 Additional ThumbEE instructions ................................................... A9-14

Part B System Level Architecture

Chapter B1 The System Level Programmers' Model

B1.1 About the system level programmers' model ................................... B1-2 B1.2 System level concepts and terminology ........................................... B1-3 B1.3 ARM processor modes and core registers ....................................... B1-6

B1.4 Instruction set states ...................................................................... B1-23

B1.5 The Security Extensions ................................................................ B1-25

B1.6 Exceptions ..................................................................................... B1-30

B1.7 Coprocessors and system control .................................................. B1-62 B1.8 Advanced SIMD and floating-point support .................................... B1-64 B1.9 Execution environment support ..................................................... B1-73

Contents

viiiCopyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved.ARM DDI 0406B Chapter B2 Common Memory System Architecture Features B2.1 About the memory system architecture ........................................... B2-2

B2.2 Caches ............................................................................................. B2-3

B2.3 Implementation defined memory system features ......................... B2-27 B2.4 Pseudocode details of general memory system operations .......... B2-29 Chapter B3 Virtual Memory System Architecture (VMSA)

B3.1 About the VMSA .............................................................................. B3-2

B3.2 Memory access sequence ............................................................... B3-4

B3.3 Translation tables ............................................................................. B3-7

B3.4 Address mapping restrictions ......................................................... B3-23 B3.5 Secure and Non-secure address spaces ....................................... B3-26 B3.6 Memory access control .................................................................. B3-28 B3.7 Memory region attributes ............................................................... B3-32 B3.8 VMSA memory aborts .................................................................... B3-40 B3.9 Fault Status and Fault Address registers in a VMSA implementation ...... B3-48 B3.10 Translation Lookaside Buffers (TLBs) ............................................ B3-54 B3.11 Virtual Address to Physical Address translation operations ........... B3-63 B3.12 CP15 registers for a VMSA implementation .................................. B3-64 B3.13 Pseudocode details of VMSA memory system operations .......... B3-156 Chapter B4 Protected Memory System Architecture (PMSA)

B4.1 About the PMSA .............................................................................. B4-2

B4.2 Memory access control .................................................................... B4-9 B4.3 Memory region attributes ............................................................... B4-11 B4.4 PMSA memory aborts .................................................................... B4-13 B4.5 Fault Status and Fault Address registers in a PMSA implementation ...... B4-18 B4.6 CP15 registers for a PMSA implementation .................................. B4-22 B4.7 Pseudocode details of PMSA memory system operations ............ B4-79

Chapter B5 The CPUID Identification Scheme

B5.1 Introduction to the CPUID scheme .................................................. B5-2

B5.2 The CPUID registers ........................................................................ B5-4

B5.3 Advanced SIMD and VFP feature identification registers .............. B5-34

Chapter B6 System Instructions

B6.1 Alphabetical list of instructions ......................................................... B6-2

Part C Debug Architecture

Chapter C1 Introduction to the ARM Debug Architecture C1.1 Scope of part C of this manual ......................................................... C1-2 C1.2 About the ARM Debug architecture ................................................. C1-3

Contents

ARM DDI 0406BCopyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved.ix C1.3 Security Extensions and debug ....................................................... C1-8

C1.4 Register interfaces ........................................................................... C1-9

Chapter C2 Invasive Debug Authentication

C2.1 About invasive debug authentication ............................................... C2-2

Chapter C3 Debug Events

C3.1 About debug events ......................................................................... C3-2

C3.2 Software debug events .................................................................... C3-5

C3.3 Halting debug events ..................................................................... C3-38

C3.4 Generation of debug events ........................................................... C3-40

C3.5 Debug event prioritization .............................................................. C3-43

Chapter C4 Debug Exceptions

C4.1 About debug exceptions .................................................................. C4-2 C4.2 Effects of debug exceptions on CP15 registers and the DBGWFAR ........ C4-4

Chapter C5 Debug State

C5.1 About Debug state ........................................................................... C5-2

C5.2 Entering Debug state ....................................................................... C5-3

C5.3 Behavior of the PC and CPSR in Debug state ................................. C5-7 C5.4 Executing instructions in Debug state .............................................. C5-9

C5.5 Privilege in Debug state ................................................................. C5-13

C5.6 Behavior of non-invasive debug in Debug state ............................. C5-19 C5.7 Exceptions in Debug state ............................................................. C5-20 C5.8 Memory system behavior in Debug state ....................................... C5-24

C5.9 Leaving Debug state ...................................................................... C5-28

Chapter C6 Debug Register Interfaces

C6.1 About the debug register interfaces ................................................. C6-2 C6.2 Reset and power-down support ....................................................... C6-4

C6.3 Debug register map ....................................................................... C6-18

C6.4 Synchronization of debug register updates .................................... C6-24

C6.5 Access permissions ....................................................................... C6-26

C6.6 The CP14 debug register interfaces .............................................. C6-32 C6.7 The memory-mapped and recommended external debug interfaces ....... C6-43

Chapter C7 Non-invasive Debug Authentication

C7.1 About non-invasive debug authentication ........................................ C7-2 C7.2 v7 Debug non-invasive debug authentication .................................. C7-4 C7.3 Effects of non-invasive debug authentication .................................. C7-6 C7.4 ARMv6 non-invasive debug authentication ...................................... C7-8

Contents

xCopyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved.ARM DDI 0406B

Chapter C8 Sample-based Profiling

C8.1 Program Counter sampling .............................................................. C8-2

Chapter C9 Performance Monitors

C9.1 About the performance monitors ...................................................... C9-2 C9.2 Status in the ARM architecture ........................................................ C9-4 C9.3 Accuracy of the performance monitors ............................................ C9-5

C9.4 Behavior on overflow ....................................................................... C9-6

C9.5 Interaction with Security Extensions ................................................ C9-7

C9.6 Interaction with trace ........................................................................ C9-8

C9.7 Interaction with power saving operations ......................................... C9-9

C9.8 CP15 c9 register map .................................................................... C9-10

C9.9 Access permissions ....................................................................... C9-12

C9.10 Event numbers ............................................................................... C9-13

Chapter C10 Debug Registers Reference

C10.1 Accessing the debug registers ....................................................... C10-2 C10.2 Debug identification registers ......................................................... C10-3 C10.3 Control and status registers ......................................................... C10-10 C10.4 Instruction and data transfer registers ......................................... C10-40 C10.5 Software debug event registers ................................................... C10-48 C10.6 OS Save and Restore registers, v7 Debug only .......................... C10-75 C10.7 Memory system control registers ................................................. C10-80 C10.8 Management registers, ARMv7 only ............................................ C10-88 C10.9 Performance monitor registers ................................................... C10-105

Appendix A Recommended External Debug Interface

A.1 System integration signals ......................................................... AppxA-2 A.2 Recommended debug slave port ............................................. AppxA-13 Appendix B Common VFP Subarchitecture Specification B.1 Scope of this appendix ............................................................... AppxB-2 B.2 Introduction to the Common VFP subarchitecture ..................... AppxB-3 B.3 Exception processing ................................................................. AppxB-6 B.4 Support code requirements ...................................................... AppxB-11 B.5 Context switching ..................................................................... AppxB-14 B.6 Subarchitecture additions to the VFP system registers ........... AppxB-15 B.7 Version 1 of the Common VFP subarchitecture ....................... AppxB-23 B.8 Version 2 of the Common VFP subarchitecture ....................... AppxB-24

Appendix C Legacy Instruction Mnemonics

C.1 Thumb instruction mnemonics ................................................... AppxC-2 C.2 Pre-UAL pseudo-instruction NOP .............................................. AppxC-3

Contents

ARM DDI 0406BCopyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved.xi

Appendix D Deprecated and Obsolete Features

D.1 Deprecated features .................................................................. AppxD-2 D.2 Deprecated terminology ............................................................. AppxD-5

D.3 Obsolete features ....................................................................... AppxD-6

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