ARM® Instruction Set Quick Reference Card
ARM® Instruction Set. Quick Reference Card. Key to Tables. {endianness}. Can be BE (Big Endian) or LE (Little Endian). {cond}. Refer to Table Condition
ARM Architecture Reference Manual
The purpose of this manual is to describe the ARM instruction set architecture including its high code density Thumb subset
ARM Instruction Set
The ARM instruction set formats are shown below. Refer to. Figure 3-6: Program status register format on page 3-12 for a full description of the.
ARM Architecture Reference Manual
The purpose of this manual is to describe the ARM instruction set architecture including its high code density Thumb® subset
ARM® and Thumb®-2 Instruction Set Quick Reference Card
ARM® and Thumb®-2 Instruction Set. Quick Reference Card. Key to Tables. Rm { <opsh>}. See Table Register
Arm® Instruction Set Reference Guide
25 oct. 2018 Use of the word “partner” in reference to Arm's customers is ... A32/T32 Instruction Set Reference. Chapter C1. Condition Codes.
Cortex-M3/M4F Instruction Set Technical Users Manual (Rev. A)
4 nov. 2011 Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others.
ARM® and Thumb®-2 Instruction Set Quick Reference Card
ARM® and Thumb®-2 Instruction Set. Quick Reference Card. Key to Tables. Rm { <opsh>} See Table Register
Instruction Set Assembly Guide for Armv7 and earlier Arm
9 oct. 2019 Use of the word “partner” in reference to Arm's customers is ... A32/T32 Instruction Set Reference. Chapter C1. Condition Codes.
ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
5 avr. 2007 No part of this ARM Architecture Reference Manual may be reproduced in any form by any means without the ... ARM instruction set encoding .
Quick Reference Card
Key to Tables
Rm {,C*, V*Flag is unpredictable in Architecture v4 and earlier, unchanged in Architecture v5 and later.+/-+ or -. (+ may be omitted.)
shown in Table Register, optionally shifted by constant.
Thumb: a 32-bit constant, formed by left-shifting an 8-bit value by any number of bits, or a bit
pattern of one of the forms 0xXYXYXYXY, 0x00XY00XY or 0xXY00XY00.
{IA|IB|DA|DB}Increment After, Increment Before, Decrement After, or Decrement Before. {!}Updates base register after data transfer if ! present (pre-indexed).
IB and DA are not available in Thumb state. If omitted, defaults to IA.{S}Updates condition flags if S present.
SB and SH are not available in STR instructions.{R}Rounds result to nearest if R present, otherwise truncates result.
Operation § Assembler S updates Action Notes
AddAddADD{S} Rd, Rn,AddressForm PC-relative addressADR Rd,
SubtractSubtractSUB{S} Rd, Rn,Exception return without stackSUBS PC, LR, #
Parallel
arithmeticHalfword-wise addition 6
Halfword-wise subtraction 6
6ADD8 Rd, Rn, RmRd[31:24] := Rn[31:24] + Rm[31:24], Rd[23:16] := Rn[23:16] + Rm[23:16],
Rd[15:8] := Rn[15:8] + Rm[15:8], Rd[7:0] := Rn[7:0] + Rm[7:0]G Byte-wise subtraction 6
Halfword-wise exchange, add, subtract 6
Halfword-wise exchange, subtract, add 6
Unsigned sum of absolute differences 6USAD8 Rd, Rm, RsRd := Abs(Rm[31:24] - Rs[31:24]) + Abs(Rm[23:16] - Rs[23:16])+ Abs(Rm[15:8] - Rs[15:8]) + Abs(Rm[7:0] - Rs[7:0])
and accumulate 6USADA8 Rd, Rm, Rs, RnRd := Rn + Abs(Rm[31:24] - Rs[31:24]) + Abs(Rm[23:16] - Rs[23:16])+ Abs(Rm[15:8] - Rs[15:8]) + Abs(Rm[7:0] - Rs[7:0])
SaturateSigned saturate word, right shift 6SSAT Rd, #
Signed saturate word, left shift 6SSAT Rd, #
Unsigned saturate word, right shift 6USAT Rd, #
Unsigned saturate word, left shift 6USAT Rd, #
ARM and Thumb-2 Instruction Set
Quick Reference Card
Operation § Assembler S updates Action Notes
MultiplyMultiplyMUL{S} Rd, Rm, RsN Z C* Rd := (Rm * Rs)[31:0] (If Rm is Rd, S can be used in Thumb-2) N, S
and accumulateMLA{S} Rd, Rm, Rs, RnN Z C* Rd := (Rn + (Rm * Rs))[31:0] S and subtract T2MLS Rd, Rm, Rs, RnRd := (Rn - (Rm * Rs))[31:0] unsigned longUMULL{S} RdLo, RdHi, Rm, RsN Z C* V* RdHi,RdLo := unsigned(Rm * Rs) Sunsigned accumulate longUMLAL{S} RdLo, RdHi, Rm, RsN Z C* V* RdHi,RdLo := unsigned(RdHi,RdLo + Rm * Rs) S
unsigned double accumulate long 6UMAAL RdLo, RdHi, Rm, RsRdHi,RdLo := unsigned(RdHi + RdLo + Rm * Rs)
Signed multiply longSMULL{S} RdLo, RdHi, Rm, RsN Z C* V* RdHi,RdLo := signed(Rm * Rs) S and accumulate longSMLAL{S} RdLo, RdHi, Rm, RsN Z C* V* RdHi,RdLo := signed(RdHi,RdLo + Rm * Rs) S16 * 16 bit 5ESMULxy Rd, Rm, RsRd := Rm[x] * Rs[y]
32 * 16 bit 5ESMULWy Rd, Rm, RsRd := (Rm * Rs[y])[47:16]
16 * 16 bit and accumulate 5ESMLAxy Rd, Rm, Rs, RnRd := Rn + Rm[x] * Rs[y] Q
32 * 16 bit and accumulate 5ESMLAWy Rd, Rm, Rs, RnRd := Rn + (Rm * Rs[y])[47:16] Q
16 * 16 bit and accumulate long 5ESMLALxy RdLo, RdHi, Rm, RsRdHi,RdLo := RdHi,RdLo + Rm[x] * Rs[y]
Dual signed multiply, add 6SMUAD{X} Rd, Rm, RsRd := Rm[15:0] * RsX[15:0] + Rm[31:16] * RsX[31:16] Q and accumulate 6SMLAD{X} Rd, Rm, Rs, RnRd := Rn + Rm[15:0] * RsX[15:0] + Rm[31:16] * RsX[31:16] Qand accumulate long 6SMLALD{X} RdLo, RdHi, Rm, RsRdHi,RdLo := RdHi,RdLo + Rm[15:0] * RsX[15:0] + Rm[31:16] * RsX[31:16]
Dual signed multiply, subtract 6SMUSD{X} Rd, Rm, RsRd := Rm[15:0] * RsX[15:0] - Rm[31:16] * RsX[31:16] Q
and accumulate 6SMLSD{X} Rd, Rm, Rs, RnRd := Rn + Rm[15:0] * RsX[15:0] - Rm[31:16] * RsX[31:16] Qand accumulate long 6SMLSLD{X} RdLo, RdHi, Rm, RsRdHi,RdLo := RdHi,RdLo + Rm[15:0] * RsX[15:0] - Rm[31:16] * RsX[31:16]
Signed top word multiply 6SMMUL{R} Rd, Rm, RsRd := (Rm * Rs)[63:32] and accumulate 6SMMLA{R} Rd, Rm, Rs, RnRd := Rn + (Rm * Rs)[63:32] and subtract 6SMMLS{R} Rd, Rm, Rs, RnRd := Rn - (Rm * Rs)[63:32] with internal 40-bit accumulate XSMIA Ac, Rm, RsAc := Ac + Rm * Rs packed halfword XSMIAPH Ac, Rm, RsAc := Ac + Rm[15:0] * Rs[15:0] + Rm[31:16] * Rs[31:16] halfword XSMIAxy Ac, Rm, RsAc := Ac + Rm[x] * Rs[y] DivideSigned or Unsigned RM40-bit accumulator to register XS
MRA RdLo, RdHi, AcRdLo := Ac[31:0], RdHi := Ac[39:32] register to 40-bit accumulator XSMAR Ac, RdLo, RdHiAc[31:0] := RdLo, Ac[39:32] := RdHiShiftArithmetic shift rightASR{S} Rd, Rm,
Logical shift leftLSL{S} Rd, Rm,
Logical shift rightLSR{S} Rd, Rm,
ARM and Thumb-2 Instruction Set
Quick Reference Card
Operation § Assembler ActionNotes
Bit fieldBit Field Clear T2BFC Rd, #
Bit Field Insert T2BFI Rd, Rn, #
Signed Bit Field Extract T2SBFX Rd, Rn, #
Unsigned Bit Field Extract T2UBFX Rd, Rn, #
PackPack halfword bottom + top 6PKHBT Rd, Rn, Rm{, LSL #
Pack halfword top + bottom 6PKHTB Rd, Rn, Rm{, ASR #
Signed
extendHalfword to word 6SXTH Rd, Rm{, ROR #
Two bytes to halfwords 6SXTB16 Rd, Rm{, ROR #
Unsigned
extendHalfword to word 6UXTH Rd, Rm{, ROR #
Signed
extendwith addHalfword to word, add 6SXTAH Rd, Rn, Rm{, ROR #
Two bytes to halfwords, add 6SXTAB16 Rd, Rn, Rm{, ROR #
Byte to word, add 6SXTAB Rd, Rn, Rm{, ROR #
Unsigned
extendwith addHalfword to word, add 6UXTAH Rd, Rn, Rm{, ROR #
Two bytes to halfwords, add 6UXTAB16 Rd, Rn, Rm{, ROR #
Byte to word, add 6UXTAB Rd, Rn, Rm{, ROR #
Bytes in word 6REV Rd, RmRd[31:24] := Rm[7:0], Rd[23:16] := Rm[15:8], Rd[15:8] := Rm[23:16], Rd[7:0] := Rm[31:24] N
Bytes in both halfwords 6REV16 Rd, RmRd[15:8] := Rm[7:0], Rd[7:0] := Rm[15:8], Rd[31:24] := Rm[23:16], Rd[23:16] := Rm[31:24] N
Bytes in low halfword,
sign extend6REVSH Rd, RmRd[15:8] := Rm[7:0], Rd[7:0] := Rm[15:8], Rd[31:16] := Rm[7] * &FFFF N SelectSelect bytes 6SEL Rd, Rn, RmRd[7:0] := Rn[7:0] if GE[0] = 1, else Rd[7:0] := Rm[7:0] Bits[15:8], [23:16], [31:24] selected similarly by GE[1], GE[2], GE[3]If-ThenIf-Then T2IT{pattern} {cond}Makes up to four following instructions conditional, according to pattern. pattern is a string of up to three
letters. Each letter can be T (Then) or E (Else).The first instruction after IT has condition cond. The following instructions have condition cond if the
corresponding letter is T, or the inverse of cond if the corresponding letter is E. See Table Condition Field for available condition codes.T UBranchBranchB
with linkBL
with link and exchange (1) 5TBLX
with link and exchange (2) 5BLX RmLR := address of next instruction, PC := Rm[31:1]. Change to Thumb if Rm[0] is 1, to ARM if Rm[0] is 0. N
and change to Jazelle state 5JBXJ RmChange to Jazelle state if availableCompare, branch if (non) zero T2CB{N}Z Rn,
Table Branch Byte T2TBB [Rn, Rm]PC = PC + ZeroExtend( Memory( Rn + Rm, 1) << 1). Branch range 4-512. Rn can be PC. T U
Table Branch Halfword T2TBH [Rn, Rm, LSL #1]PC = PC + ZeroExtend( Memory( Rn + Rm << 1, 2) << 1). Branch range 4-131072. Rn can be PC. T U
Move to or
from PSRPSR to registerMRS Rd,Processor
statechangeChange processor state 6CPSID
6CPSIE {, #}Enable specified interrupts, optional change mode. U, N
Change processor mode 6CPS #U
Set endianness 6SETEND
ARM Instruction Set
Quick Reference Card
Single data item loads and stores § Assembler Action ifor halfwordImmediate offset
Post-indexed, immediate
Register offset
Post-indexed, register
Load or store
doublewordImmediate offset 5E
Post-indexed, immediate 5E
Register offset 5E
Post-indexed, register 5E
Preload data or instruction § (PLD) § (PLI) Assembler Action if
Immediate offset 5E 7
Register offset 5E 7
Load multipleBlock data loadLDM{IA|IB|DA|DB} Rn{!},
return (and exchange)LDM{IA|IB|DA|DB} Rn{!},
and restore CPSRLDM{IA|IB|DA|DB} Rn{!},
User mode registersLDM{IA|IB|DA|DB} Rn,
exclusiveSemaphore operation 6LDREX Rd, [Rn]Rd := [Rn], tag address as exclusive access. Outstanding tag set if not shared address.Rd, Rn not PC.
Halfword or Byte 6KLDREX{H|B} Rd, [Rn]Rd[15:0] := [Rn] or Rd[7:0] := [Rn], tag address as exclusive access. Outstanding tag set if not shared address. Rd, Rn not PC.
Doubleword 6KLDREXD Rd1, Rd2, [Rn]Rd1 := [Rn], Rd2 := [Rn+4], tag addresses as exclusive access Outstanding tags set if not shared addresses. Rd1, Rd2, Rn not PC.9Store multiplePush, or Block data storeSTM{IA|IB|DA|DB} Rn{!},
User mode registersSTM{IA|IB|DA|DB} Rn{!},
exclusiveSemaphore operation 6STREX Rd, Rm, [Rn]If allowed, [Rn] := Rm, clear exclusive tag, Rd := 0. Else Rd := 1. Rd, Rm, Rn not PC.
Halfword or Byte 6KSTREX{H|B} Rd, Rm, [Rn]If allowed, [Rn] := Rm[15:0] or [Rn] := Rm[7:0], clear exclusive tag, Rd := 0. Else Rd := 1
Rd, Rm, Rn not PC.
Doubleword 6KSTREXD Rd, Rm1, Rm2, [Rn]If allowed, [Rn] := Rm1, [Rn+4] := Rm2, clear exclusive tags, Rd := 0. Else Rd := 1
Rd, Rm1, Rm2, Rn not PC.9
Clear exclusive6KCLREXClear local processor exclusive tag C Notes: availability and range of options for Load, Store, and Preload operationsNote ARM Word, B, D ARM SB, H, SH ARM T, BT Thumb-2 Word, B, SB, H, SH, D Thumb-2 T, BT, SBT, HT, SHT
1 offset: - 4095 to +4095 offset: -255 to +255 Not available offset: -255 to +255 if writeback, -255 to +4095 otherwise offset: 0 to +255, writeback not allowed
2 offset: - 4095 to +4095 offset: -255 to +255 offset: - 4095 to +4095 offset: -255 to +255 Not available
3 Full range of {, } {, } not allowed Not available restricted to LSL #, range 0 to 3 Not available
4 Full range of {, } {, } not allowed Full range of {, }Not available Not available
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