[PDF] Gigabit Ethernet Switch Subsystem for KeyStone Devices Users





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Gigabit Ethernet Switch Subsystem for KeyStone Devices Users www.ti.com www.ti.com www.ti.com www.ti.com www.ti.com www.ti.com www.ti.com www.ti.com www.ti.com www.ti.com www.ti.com www.ti.com www.ti.com

3-Port

Ethernet

Switch

MDIO SGMII SGMII

SGMII0 Port

(Switch Port 1)

SGMII1 Port

(Switch Port 2)

SerDes

SerDes

Configuration BusTo External Pins

SGMII 0

SGMII 1PHY

MDIO

InterruptsSwitch

Interrupts

Host Port

(Switch Port 0)

KeyStone I

Ethernet Switch

Subsystem

To NETCPTo Host

5-Port

Ethernet

Switch

MDIO SGMII SGMII

SGMII0 Port

(Switch Port 1)

SGMII1 Port

(Switch Port 2)

SerDes

SerDes

Configuration BusTo External Pins

SGMII 0

SGMII 1PHY

MDIO

InterruptsSwitch

Interrupts

Host Port

(Switch Port 0)

KeyStone II

Ethernet Switch

Subsystem

To NETCPTo Host

SGMII SGMII

SGMII2 Port

(Switch Port 3)

SGMII3 Port

(Switch Port 4)

SerDes

SerDes

SGMII 2

SGMII 3

Port1SGMIImodule100h

Port2SGMIImodule200h

MDIOmodule300h

Reserved400h-7FFh

GigabitEthernet(GbE)switchmodule800h

(1)

Port1SGMIImodule100h

Port2SGMIImodule200h

MDIOmodule300h

Port3SGMIImodule400h

Port4SGMIImodule500h

Reserved600h-7FFh

GigabitEthernet(GbE)switchmodule800h

BitsFieldDescription

BitsFieldDescription

www.ti.comGigabitEthernetSwitchArchitecture33SPRUGV9D-November2010-RevisedJune2013SubmitDocumentationFeedbackCopyright©2010-2013,TexasInstrumentsIncorporatedArchitecture2.3.4StatisticsSubmoduleArchitectureThissectiondescribesthearchitectureofthestatisticsmodulesintheGbEswitch(seeSection3.5.4.)TheGbEswitchhastwosetsofstatisticsmodulesthatrecordeventsassociatedwithpacketsenteringandexitingtheswitch.ThestatisticsforKeyStoneIswitchport0arerecordedonstatisticsmoduleA(STATSA),andstatisticsforports1and2arerecordedonstatisticsmoduleB(STATSB).ForKeyStoneIIdevices,theadditionalportsarerecordedintheadditionalstatisticsmodulesSTATSCandSTATSD.Eachstatisticregisteris32-bitswideandautomaticallyincrementswhenacertainstatisticsconditionismet.Eachstatisticwillrolloverfrom0xFFFFFFFFto0x00000000.ForKeystoneII,theEthernetswitchhasfoursetsofstatisticsthatrecordeventsassociatedwithframetrafficonselectedswitchports.STATSAkeepsstatisticsforport0receive,port0TXA,andport0TXB.STATSCkeepsstatisticsforport0TXCandport0TXD(STATSCreceivestatisticsareunused).STATSBkeepsstatisticsforport1andSTATSDkeepsstatisticsforports3and4.Thestatisticsarepagedintheaddressmap.STATSA/Bstatisticsarevisibleintheaddressrangewhenstat_selisclearedto0intheStat_PortRegister.STATSC/Dstatisticsarevisibleintheaddressrangewhenstat_selissetto1intheStat_PortRegister.NOTE:ToviewtheSTATSfortheSTATSmodule,theymustfirstbeenabledintheStatsConfigurationRegister.KeyStoneIdeviceshaveonlySTATSAandSTATSB - noSTATSCorSTATSD.KeyStoneIIdeviceshaveSTATSAandSTATSB,plusSTATSCandSTATSD.STATSAandSTATSCsharethesameaddressspace,andSTATSBandSTATSDsharethesameaddressspace.TheusermustconfiguretheSTATSenableregister(StaticsportEnableRegisterSTAT_PORT_EN--Section3.5.1.4)topickwhichofthepairofSTATSmodulestoview - eitherSTATSA/STATSBforport0andport1,orSTATSC/STATSDforport2andport3.Allfourcannotbeviewedatthesametimebecausetheysharethesameaddressspace.2.3.4.1AccessingStatisticsRegistersThissectiondescribeshowtocorrectlyreadandwritetotheregistersinthestatisticsmoduleswhilethemodulesaredisabledorenabled.Bydefault,thestatisticsmodulesaredisabled.Whiledisabled,allstatisticsregisterscanbereadandwrittennormally,sowriting0x00000000clearsastatisticsregister.Afterthestatisticsmodulesareenabled,allstatisticscanstillbereadnormally;however,registerwriteswillbecomewritetodecrement,meaningthatthevaluewrittentotheregisterwillbesubtractedfromtheregistervalue,withtheresultbeingstoredintheregister(newregistervalue=oldregistervalue-writevalue).Ifthevaluewrittenisgreaterthanthevalueinthestatisticsregister,then0willbewrittentothatregister.Whenastatisticsmoduleisenabled,writingavalueof0xFFFFFFFFwillclearastatisticslocation.Whenwritingtoastatisticsregister,32-bitaccessesmustbeused.Thestatisticsmodulescanbeenabledbywritingtobits3:0theSTAT_PORT_ENRegister.2.3.4.2StatisticsInterruptsThissectiondescribesinterruptsgeneratedbythestatisticsmodules.ForKeyStoneI,eachofthetwostatisticsmoduleshavetheabilitytosendaninterrupttothehost.TheinterruptfortheSTATSAmodulewilloccurontheSTAT_PEND_RAW[0]signal,andtheinterruptfortheSTATSBmodulewilloccurontheSTAT_PEND_RAW[1]signal.Theinterruptwillbetriggeredwhenanyofthevaluesinthestatisticsregistersbecomegreaterthanorequalto0x80000000.Thestatisticsinterruptcanberemovedbywritingavaluegreaterthan0x80000000.ForKeyStoneIIdevices,STAT_PEND_RAWisa4-bitvalue,withthethirdandfourthbitrepresentingSTATSCandSTATSDrespectively.

Block0

Secure0

ReservedENTRY_TYPEReserved

ENTRY_TYPE[1:0]00

ReservedPORT_MASKSUPERRsvdMCAST_FWD_

STATEENTRY_TYPEReservedMULTICAST

_ADDRESS

MULTICAST_ADDRESS[47:0]Userconfigurable

ReservedPORT_MASKSUPERRsvdMCAST_FWD

_STATEENTRY_TYPEVLAN_IDMULTICAST _ADDRESS

ReservedPORT

_NUMBERBLOCKSECUREUNICAST _TYPEENTRY_TYPEReservedUNICAST_ADDRESS

UNICAST_ADDRESS[47:0]Userconfigurable

ReservedUNICAST

_TYPEENTRY_TYPEReservedUNICAST _OUIReserved

FieldNameConfiguration

UNICAST_TYPE[1:0]10

ENTRY_TYPE[1:0]01

ReservedPORT

_NUMBERBLOCKSECUREUNICAST _TYPEENTRY_TYPEVLAN_IDUNICAST_ADDRESS

ReservedENTRY

_TYPEVLAN_IDReservedFORCE _UNTAG

GED_EG

RESSReservedREG

_MCAST _FLOOD _MASKReservedUNREG _MCAST _FLOOD _MASKReservedVLAN _MEMBER _LIST

ENTRY_TYPE[1:0]10

MAC SGMII

SerDesSerDes

SGMII GMAC

MASTERSLAVE

MAC SGMII

SerDesPHY

8B/10B

MAC SGMII

SerDesSerDes

SGMII MAC

MASTERMASTER

Address

(1)ModuleAcronymRegisterNameSection

120hPort1SGMIISGMII_MR_LP_ADV

Address

(1)ModuleAcronymRegisterNameSection

220hPort2SGMIISGMII_MR_LP_ADV

3.5.1.10

Address

(1)ModuleAcronymRegisterNameSection

3.5.1.11

3.5.1.12

844h-

805ChReservedReservedReservedReserved

3.5.1.13

3.5.1.14

3.5.1.15

3.5.1.16

3.5.1.17

3.5.1.18

3.5.1.19

3.5.1.20

3.5.1.21

884h-

808ChReservedReservedReservedReserved

3.5.1.24

3.5.1.25

3.5.1.26

3.5.1.27

3.5.1.28

3.5.1.29

3.5.1.30

3.5.1.32

Address

(1)ModuleAcronymRegisterNameSection

3.5.4.10

B28h-B2FhSTATSAReservedReservedReserved

3.5.4.11

3.5.4.12

B38hSTATSATXBROADCAST

3.5.4.13

B3ChSTATSATXMULTICAST

3.5.4.14

3.5.4.15

B44hSTATSATXDEFERRED

FRAMESTotalnumberofframesdeferredSection

3.5.4.16

B48hSTATSATXCOLLISION

FRAMESTotalnumberofcollisionsSection

3.5.4.17

B4ChSTATSATXSINGLECOLL

3.5.4.18

B50hSTATSATXMULTCOLL

3.5.4.19

B54hSTATSATXEXCESSIVE

3.5.4.20

3.5.4.21

Address

(1)ModuleAcronymRegisterNameSection

3.5.4.22

B60hSTATSATXCARRIERSENSEE

3.5.4.23

3.5.4.24

3.5.4.25

B6ChSTATSA65T127OCTET

3.5.4.26

B70hSTATSA128T255OCTET

3.5.4.27

B74hSTATSA256T511OCTET

3.5.4.28

B78hSTATSA512T1023OCTET

3.5.4.29

B7ChSTATSA1024TUPOCTET

3.5.4.30

3.5.4.31

3.5.4.32

3.5.4.33

3.5.4.34

3.5.4.10

3.5.4.11

3.5.4.12

C38hSTATSBTXBROADCAST

3.5.4.13

C3ChSTATSBTXMULTICAST

3.5.4.14

3.5.4.15

Address

(1)ModuleAcronymRegisterNameSection

C44hSTATSBTXDEFERRED

FRAMESTotalnumberofframesdeferredSection

3.5.4.16

C48hSTATSBTXCOLLISION

FRAMESTotalnumberofcollisionsSection

3.5.4.17

C4ChSTATSBTXSINGLECOLL

3.5.4.18

C50hSTATSBTXMULTCOL

3.5.4.19

C54hSTATSBTXEXCESSIVE

3.5.4.20

3.5.4.21

3.5.4.22

C60hSTATSBTXCARRIERSENSE

3.5.4.23

3.5.4.24

3.5.4.25

C6ChSTATSB65T127OCTET

3.5.4.26

C70hSTATSB128T255OCTET

3.5.4.27

C74hSTATSB256T511OCTET

3.5.4.28

C78hSTATSB512T1023OCTET

3.5.4.29

C7ChSTATSB1024TUPOCTET

3.5.4.30

3.5.4.31

3.5.4.32

3.5.4.33

3.5.4.34

C90h-

CFChReservedReservedReservedReserved

D1ChReservedReservedReservedReserved

Address

(1)ModuleAcronymRegisterNameSection

3.5.5.11

D3Ch-

DFChReservedReservedReservedReserved

E18hALEALE_UNKNOWN

3.5.6.10

3.5.6.11

E4Ch-

FFChReservedReservedReservedReserved

Address

(1)ModuleAcronymRegisterNameSection

Address

(1)ModuleAcronymRegisterNameSection

41ChReservedReservedReservedReserved

Address

(1)ModuleAcronymRegisterNameSection

Address

(1)ModuleAcronymRegisterNameSection

Address

(1)ModuleAcronymRegisterNameSection

C00hSTATSB/

Address

(1)ModuleAcronymRegisterNameSection

Address

(1)ModuleAcronymRegisterNameSection

Address

(1)AcronymRegisterNameSection

ES_SS_IDENT

R-4ED9h

151110870

R-0hR-0hR-8h

BitsFieldDescription

SGMII_IDENT

R-4EC2h

151110870

R-0hR-1hR-1h

ReservedRT_SOFT

_RESETSOFT _RESET

R-0hR/W-0hR/W-0h

31-2ReservedReserved

ReservedMASTERLOOP

BACKReservedMR_AN

_RESTARTMR_AN _ENABLE

R-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0h

31-6ReservedReserved

ReservedLOCKReservedMR_AN

_COMPLETEAN _ERRORLINK

R-0R-0R-0R-0R-0R-0

31-5ReservedReserved

2MR_AN_COMPLE

ReservedMR_ADV_ABILITY

R-0R/W-0

31-16ReservedReserved

TX_CONFIG_REG[15-0]MACPHY

15Link.

•0=Linkisdown•1=Linkisup0

14auto-negotiationacknowledge1

1300

11-10Speed.

9-100 011

ReservedMR_LP_ADV_ABILITY

R-0R-0

BitsFieldDescription

31-16ReservedReserved

Address

(1)AcronymRegisterNameSection

MDIO_MODIDMDIO_REVMAJMDIO_REVMIN

R-7hR-1hR-4h

IDLEENABLERsvdHIGHEST_USER

_CHANReservedPREAMB

LEFAULT

SFAULTEN

BReserved

R-1R/W-0R-0R-1R-0R/W-0R/W-0R/W-0R-0

150

CLKDIV

R/W-00FFh

ALIVE

R/W-0h

LINK R-0h

ReservedLINKINTRAW

R-0hR/W-0h

BitsFieldDescription

31-2ReservedReserved

ReservedLINKINTMASK

ED

R-0hR/W-0h

BitsFieldDescription

31-2ReservedReserved

ReservedUSERINTRAW

R-0hR/W-0h

31-2ReservedReserved

ReservedUSERINT

MASKED

R-0hR/W-0h

31-2ReservedReserved

31210

ReservedUSERINT

MASKSET

R-0hR/W-0h

31-2ReservedReserved

31210

ReservedUSERINT

MASKCLEAR

R-0hR/W-0h

31-2ReservedReserved

GOWRIT

EACKReservedREGADRPHYADR

R/W-

0hR/W-

0hR/W-

0hR-0hR/W-0hR/W-0h

150
DATA

R/W-0h

ReservedLINKSELLINKINT

ENBReservedPHYADR_MON

R-0hR/W-0hR/W-0hR-0hR/W-0h

31-8ReservedReserved

GOWRIT

EACKReservedREGADRPHYADR

R/W-

0hR/W-

0hR/W-

0hR-0hR/W-0hR/W-0h

150
DATA

R/W-0h

ReservedLINKSELLINKINT

ENBReservedPHYADR_MON

R-0hR/W-0hR/W-0hR-0hR/W-0h

31-8ReservedReserved

Address

(1)AcronymSubmoduleNameSection

Address

(1)AcronymSubmoduleNameSection

Address

(1)AcronymDescriptionSection

Address

(1)AcronymDescriptionSection

Address

(1)AcronymDescriptionSection

CPSW_IDVER

R-4ED801h

151110870

CPSW_RTL_VERCPSW_MAJ_VERCPSW_MINOR_VER

R-0hR-1hR-1h

R-0R/W-0R/W-0R-0

543210

R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0

31-9ReservedReserved

ReservedSOFTFREE

R-0R/W-0R/W-0

31-2ReservedReserved

R-0R/W-0R/W-0R/W-0R/W-0

31-4ReservedReserved

ReservedSTAT_SELReserved

R-0R/W-0R-0

76543210

R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0

31-29ReservedReserved

ReservedP2_PTYPE

_ESCP1_PTYPE _ESCP0_PTYPE _ESCReservedESC_PRI_LD_VAL

R-0R/W-0R/W-0R/W-0R/W-0R/W-0

31-11ReservedReserved

ReservedP4_PTYPE

_ESCP3_PTYPE _ESCP2_PTYPE _ESCP1_PTYPE_ESCReservedESC_PRI_LD_VAL

R-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0

31-13ReservedReserved

ReservedGAP_THRESH

R-0R/W-Bh

BitsFieldDescription

31-5ReservedReserved

ReservedTS_START_WDS

R-0R/W-20h

31-11ReservedReserved

ReservedP2_FLOW_ENP1_FLOW_ENP0_FLOW_EN

R-0R/W-0R/W-0R/W-1

31-3ReservedReserved

R-0R/W-0R/W-0R/W-0R/W-0R/W-1

31-5ReservedReserved

ReservedTXB_SCR_IDTXA_SRC_ID

R-0R/W-2hR/W-1h

quotesdbs_dbs29.pdfusesText_35
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