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NVM Express

TM

Revision 1.4

1

NVM Express

TM

Base Specification

NVM Express

Revision 1.4

June 10, 2019

Please send comments to info@nvmexpress.org

NVM Express

TM

Revision 1.4

2

NVM Express

TM base specification revision 1.4 is available for download at http://nvmexpress.org. The

NVM Express base specification revision 1.4 incorporates NVM Express base specification revision 1.3,

ratified on April 26, 2017, ECN 001, ECN 002, ECN 003, ECN 004a, ECN 005, ECN 006, TP 4000a, TP

4002, TP 4003c, TP 4004b, TP 4005c, TP 4006, TP 4007a, TP 4008, TP 4014, TP 4016, TP 4018b, TP

4022, TP 4024, TP 4025, TP 4027, TP 4028a, TP 4030, TP 4031a, TP 4032, TP 4033, TP 4035, TP

4039a, TP 4042a, TP 4045, TP 4050, TP 4051, TP 4054, and TP 8002 (refer to

https://nvmexpress.org/changes-in-nvme-revision-1-4 for details). Applied the NVM Express trademark and logo usage guidelines.

SPECIFICATION DISCLAIMER

LEGAL NOTICE:

© Copyright 2007 to 2019 NVM Express, Inc. ALL RIGHTS RESERVED.

This NVM Express base specification revision 1.4 is proprietary to the NVM Express, Inc. (also referred to

as "Company") and/or its successors and assigns.

NOTICE TO USERS WHO ARE NVM EXPRESS, INC. MEMBERS

: Members of NVM Express, Inc. have

the right to use and implement this NVM Express base specification revision 1.4 subject, however, to the

Member's continued compliance with the Company's Intellectual Property Policy and Bylaws and the

Member's Participation Agreement.

NOTICE TO NON

-MEMBERS OF NVM EXPRESS, INC.: If you are not a Member of NVM Express, Inc. and you have obtained a copy of this document, you only have a right to review this document or make

reference to or cite this document. Any such references or citations to this document must acknowledge

NVM Express, Inc. copyright ownership

of this document. The proper copyright citation or reference is as follows: "© 2007 to 2019 NVM Express, Inc. ALL RIGHTS RESERVED." When making any such citations or references to this document you are not permitted to revise, alter, modify, make any

derivatives of, or otherwise amend the referenced portion of this document in any way without the prior

express written permission of NVM Express, Inc. Nothing contained in this document shall be deemed as

granting you any kind of license to implement or use th is document or the specification described therein,

or any of its contents, either expressly or impliedly, or to any intellectual property owned or controlled by

NVM Express, Inc., including, without limitation, any trademarks of NVM Express, Inc.

LEGAL DISCLAIMER:

THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN IS PROVIDED ON AN "AS IS" BASIS. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, NVM EXPRESS, INC. (ALONG WITH THE CONTRIBUTORS TO THIS DOCUMENT) HEREBY DISCLAIM ALL REPRESENTATIONS, WARRANTIES AND/OR COVENANTS, EITHER EXPRESS OR IMPLIED, STATUTORY OR AT COMMON LAW, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, VALIDITY,

AND/OR NONINFRINGEMENT.

All product names, trademarks, registered trademarks, and/or servicemarks may be claimed as the property of their re spective owners.

The NVM Express

design mark is a registered trademark of NVM Express, Inc.

PCI-SIG

and PCIe are registered trademarks of PCI-SIG.

NVM Express Workgroup

c/o VTM, Inc.

3855 SW 153

rd Drive

Beaverton, OR 97003

USA info@nvmexpress.org

NVM Express

TM

Revision 1.4

3

Table of Contents

1 INTRODUCTION ............................................................................................................. 6

1.1 Overview ........................................................................................................................................ 6

1.2 Scope............................................................................................................................................. 6

1.3 Outside of Scope ........................................................................................................................... 6

1.4 Theory of Operation ....................................................................................................................... 7

1.5 Conventions ................................................................................................................................. 12

1.6 Definitions .................................................................................................................................... 13

1.7 Keywords ..................................................................................................................................... 18

1.8 Byte, Word, and Dword Relationships ......................................................................................... 19

1.9 References .................................................................................................................................. 19

1.10 References Under Development ................................................................................................. 20

2 SYSTEM BUS (PCI EXPRESS) REGISTERS ....................................................................... 21

2.1 PCI Header .................................................................................................................................. 21

2.2 PCI Power Management Capabilities .......................................................................................... 26

2.3 Message Signaled Interrupt Capability (Optional) ....................................................................... 28

2.4 MSI-X Capability (Optional) ......................................................................................................... 29

2.5 PCI Express Capability ................................................................................................................ 31

2.6 Advanced Error Reporting Capability (Optional) ......................................................................... 36

2.7 Other Capability Pointers............................................................................................................. 41

3 CONTROLLER REGISTERS ............................................................................................. 42

3.1 Register Definition ....................................................................................................................... 42

3.2 Index/Data Pair registers (Optional) ............................................................................................ 61

4 DATA STRUCTURES ..................................................................................................... 63

4.1 Submission Queue & Completion Queue Definition ................................................................... 63

4.2 Submission Queue Entry - Command Format ........................................................................... 65

4.3 Physical Region Page Entry and List .......................................................................................... 69

4.4 Scatter Gather List (SGL) ............................................................................................................ 70

4.5 Metadata Region (MR) ................................................................................................................ 76

4.6 Completion Queue Entry ............................................................................................................. 77

4.7 Controller Memory Buffer ............................................................................................................ 85

4.8 Persistent Memory Region .......................................................................................................... 86

4.9 NVM Sets .................................................................................................................................... 88

4.10 Namespace List ........................................................................................................................... 89

4.11 Controller List .............................................................................................................................. 90

4.12 Fused Operations ........................................................................................................................ 90

4.13 Command Arbitration ................................................................................................................... 91

5 ADMIN COMMAND SET ................................................................................................. 94

5.1 Abort command ........................................................................................................................... 95

5.2 Asynchronous Event Request command .................................................................................... 96

5.3 Create I/O Completion Queue command .................................................................................. 101

5.4 Create I/O Submission Queue command.................................................................................. 102

5.5 Delete I/O Completion Queue command .................................................................................. 105

5.6 Delete I/O Submission Queue command .................................................................................. 105

5.7 Doorbell Buffer Config command .............................................................................................. 106

5.8 Device Self-test command ........................................................................................................ 107

5.9 Directive Receive command ...................................................................................................... 109

5.10 Directive Send command .......................................................................................................... 110

5.11 Firmware Commit command ..................................................................................................... 111

NVM Express

TM

Revision 1.4

4

5.12 Firmware Image Download command ....................................................................................... 113

5.13 Get Features command ............................................................................................................. 114

5.14 Get Log Page command............................................................................................................ 117

5.15 Identify command ...................................................................................................................... 161

5.16 Keep Alive command ................................................................................................................. 201

5.17 NVMe-MI Receive command .................................................................................................... 201

5.18 NVMe-MI Send command ......................................................................................................... 201

5.19 Namespace Attachment command ........................................................................................... 201

5.20 Namespace Management command ........................................................................................ 202

5.21 Set Features command ............................................................................................................. 205

5.22 Virtualization Management command ....................................................................................... 232

5.23 Format NVM command - NVM Command Set Specific ........................................................... 234

5.24 Sanitize command - NVM Command Set Specific ................................................................... 236

5.25 Security Receive command - NVM Command Set Specific ..................................................... 239

5.26 Security Send command - NVM Command Set Specific ......................................................... 240

5.27 Get LBA Status command - NVM Command Set Specific ....................................................... 241

6 NVM COMMAND SET ................................................................................................. 245

6.1 Namespaces .............................................................................................................................. 246

6.2 Fused Operations ...................................................................................................................... 248

6.3 Command Ordering Requirements ........................................................................................... 249

6.4 Atomic Operations ..................................................................................................................... 249

6.5 End-to-end Protection Information ............................................................................................ 253

6.6 Compare command ................................................................................................................... 253

6.7 Dataset Management command ............................................................................................... 255

6.8 Flush command ......................................................................................................................... 258

6.9 Read command ......................................................................................................................... 258

6.10 Reservation Acquire command ................................................................................................. 261

6.11 Reservation Register command ................................................................................................ 262

6.12 Reservation Release command ................................................................................................ 263

6.13 Reservation Report command ................................................................................................... 264

6.14 Verify command ......................................................................................................................... 267

6.15 Write command ......................................................................................................................... 268

6.16 Write Uncorrectable command .................................................................................................. 271

6.17 Write Zeroes command ............................................................................................................. 272

7 CONTROLLER ARCHITECTURE ..................................................................................... 274

7.1 Introduction ................................................................................................................................ 274

7.2 Command Submission and Completion Mechanism (Informative) ........................................... 283

7.3 Resets........................................................................................................................................ 290

7.4 Queue Management .................................................................................................................. 291

7.5 Interrupts ................................................................................................................................... 292

7.6 Controller Initialization and Shutdown Processing .................................................................... 295

7.7 Asynchronous Event Request Host Software Recommendations (Informative) ....................... 297

7.8 Feature Values .......................................................................................................................... 298

7.9 NVMe Qualified Names ............................................................................................................. 299

7.10 Identifier Format and Layout (Informative) ................................................................................ 300

7.11 Unique Identifier ........................................................................................................................ 303

7.12 Keep Alive ................................................................................................................................. 304

7.13 Updating Controller Doorbell Registers using a Shadow Doorbell Buffer ................................. 306

7.14 Privileged Actions ...................................................................................................................... 306

8 FEATURES ................................................................................................................ 307

8.1 Firmware Update Process ......................................................................................................... 307

8.2 Metadata Handling .................................................................................................................... 308

NVM Express

TM

Revision 1.4

5

8.3 End-to-end Data Protection (Optional) ...................................................................................... 309

8.4 Power Management .................................................................................................................. 315

8.5 Virtualization Enhancements (Optional) .................................................................................... 320

8.6 Doorbell Stride for Software Emulation ..................................................................................... 325

8.7 Standard Vendor Specific Command Format ........................................................................... 325

8.8 Reservations (Optional) ............................................................................................................. 325

8.9 Host Memory Buffer (Optional) .................................................................................................. 332

8.10 Replay Protected Memory Block (Optional) .............................................................................. 333

8.11 Device Self-test Operations (Optional) ...................................................................................... 345

8.12 Namespace Management (Optional) ........................................................................................ 347

8.13 Boot Partitions (Optional) .......................................................................................................... 349

8.14 Telemetry (Optional) .................................................................................................................. 352

8.15 Sanitize Operations (Optional) .................................................................................................. 356

8.16 Read Recovery Level (Optional) ............................................................................................... 360

8.17 Endurance Groups .................................................................................................................... 362

8.18 Predictable Latency Mode (Optional) ........................................................................................ 363

8.19 Namespace Write Protection (Optional) .................................................................................... 367

8.20 Asymmetric Namespace Access Reporting (Optional) ............................................................. 369

8.21 Host Operation with Asymmetric Namespace Access Reporting (Informative) ........................ 376

8.22 Get LBA Status .......................................................................................................................... 378

8.23 SQ Associations (Optional) ....................................................................................................... 381

8.24 UUIDs for Vendor Specific Information ..................................................................................... 381

8.25 Improving Performance through I/O Size and Alignment Adherence ....................................... 384

9 DIRECTIVES.............................................................................................................. 390

9.1 Directive Use in I/O Commands ................................................................................................ 390

9.2 Identify (Directive Type 00h) ..................................................................................................... 391

9.3 Streams (Directive Type 01h, Optional) .................................................................................... 393

10 ERROR REPORTING AND RECOVERY .......................................................................... 400

10.1 Command and Queue Error Handling ....................................................................................... 400

10.2 Media and Data Error Handling ................................................................................................. 400

10.3 Memory Error Handling ............................................................................................................. 400

10.4 Internal Controller Error Handling .............................................................................................. 400

10.5 Controller Fatal Status Condition .............................................................................................. 401

ANNEX A. SANITIZE OPERATION CONSIDERATIONS (INFORMATIVE) ..................................... 402

A.1 Overview .................................................................................................................................... 402

A.2 Hidden Storage (Overprovisioning) ........................................................................................... 402

A.3 Integrity checks and No-Deallocate After Sanitize .................................................................... 402

A.4 Bad Block and Vendor Specific NAND Use .............................................................................. 402

NVM Express

TM

Revision 1.4

6 1

Introduction

1.1 Overview

The NVM Express

TM (NVMe TM ) interface allows host software to communicate with a non-volatile memory

subsystem. This interface is optimized for Enterprise and Client solid state drives, typically attached as a

register level interface to the PCI Express interface. Note: During development, this specification was referred to as Enterprise NVMHCI. However, the name

was modified to NVM Express base specification prior to completion. This interface is targeted for use in

both Client and Enterprise systems.

For an overview of changes from revision 1.3 to revision 1.4, refer to http://nvmexpress.org/changes for a

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