[PDF] Computer Architecture and Assembly Language





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Proposed Syllabus by C.S.J.M.UniversityKanpur. Bachelors of

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Computer Architecture and Assembly Language

Processor architecture. ? Memory. ? Memory mapping. ? Execution flow. ? Object file formats. ? Assembly programming. ? Focus on x86.



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CCS UNIVERSITY MEERUT BCA SYLLABUS

BCA-306P. BCA-307P. COURSE NAME. Object Oriented Programming Using C++ (C++). Data Structure Using C & C++ (DSC). Computer Architecture & Assembly Language 

Computer Architecture and Assembly Language

Gabriel Laskar

EPITA 2015

License

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Copyrightc

2004-2005, ACU, Benoit Perrot

I

Copyrightc

2004-2008, Alexandre Becoulet

I

Copyrightc

2009-2013, Nicolas Pouillon

I

Copyrightc

2014, Joël Porquet

I

Copyrightc

2015, Gabriel Laskar

Permission is granted to copy, distribute

and/or modify this document under the terms of the GNU Free Documentation License, Version

1.2 or any later version published by the Free

Software Foundation; with the Invariant Sections

being just ''Copying this document"", no

Front-Cover Texts, and no Back-Cover Texts.

Introduction

Part I

Introduction

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IntroductionProblem definition

1: IntroductionProblem definition

Outline

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IntroductionProblem definition

What are we trying to learn?

Computer Architecture

What is in the hardware?

I

A bit of history of computers, current machines

I Concepts and conventions: processing, memory, communication, optimization

How does a machine run code?

I

Program execution model

I

Memory mapping, OS support

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IntroductionProblem definition

What are we trying to learn?

Assembly Language

How to "talk" with the machine directly?

I

Mechanisms involved

I

Assembly language structure and usage

I

Low-level assembly language features

I

C inline assembly

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IntroductionProblem definition

Who do I talk to?I

System gurusI

Low-level enthusiastsI

ProgrammersI

Wise managers Gabriel Laskar (EPITA)CAAL 20 157 / 378

IntroductionProblem definition

Who do I talk to?I

System gurusI

Low-level enthusiastsI

ProgrammersI

Wise managers Gabriel Laskar (EPITA)CAAL 20 157 / 378

IntroductionProblem definition

Who do I talk to?I

System gurusI

Low-level enthusiastsI

Programmers

C/C++I

Wise managers Gabriel Laskar (EPITA)CAAL 20 157 / 378

IntroductionProblem definition

Who do I talk to?I

System gurusI

Low-level enthusiastsI

Programmers

C/C++,Objective-CI

Wise managers Gabriel Laskar (EPITA)CAAL 20 157 / 378

IntroductionProblem definition

Who do I talk to?I

System gurusI

Low-level enthusiastsI

Programmers

C/C++,Objective-C,C#I

Wise managers Gabriel Laskar (EPITA)CAAL 20 157 / 378

IntroductionProblem definition

Who do I talk to?I

System gurusI

Low-level enthusiastsI

Programmers

C/C++,Objective-C,C#,JavaI

Wise managers Gabriel Laskar (EPITA)CAAL 20 157 / 378

IntroductionProblem definition

Who do I talk to?I

System gurusI

Low-level enthusiastsI

Programmers

C/C++,Objective-C,C#,Java,JS/ASI

Wise managers Gabriel Laskar (EPITA)CAAL 20 157 / 378

IntroductionProblem definition

Who do I talk to?I

System gurusI

Low-level enthusiastsI

Programmers at

any level: (C/C++,Objective-C,C#,Java,JS/AS, etc.)I Wise managers Gabriel Laskar (EPITA)CAAL 20 157 / 378

IntroductionProblem definition

Who do I talk to?I

System gurusI

Low-level enthusiastsI

Programmers at

any level: (C/C++,Objective-C,C#,Java,JS/AS, etc.)I Wise managers Gabriel Laskar (EPITA)CAAL 20 157 / 378

IntroductionOutline

1: IntroductionProblem definition

Outline

Gabriel Laskar (EPITA)

CAAL

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IntroductionOutline

Course outline

I

Processor architecture

I

Memory

I

Memory mapping

I

Execution flow

I

Object file formats

I

Assembly programming

I

Focus on x86

I

Focus on RISC processors

I

CPU-aware optimizations

I

Multi-/Many-core, heterogeneous systems

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Processor architecture

Part II

Processor architecture

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Processor architectureOver view

2: Processor architectureOverview

Inside the processor

Processor units

Instructions

Instruction flow

Pipeline processor

CISC & RISC architectures

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Processor architectureOver view

What a processor is...

A processor must be able to perform the following basic tasks: I

Execute instructions

I

Read operands

I

Store results

It needs several basic units to perform those tasks: I

A control unit

I

An arithmetic and logical unit (ALU)

I

A register bankLet"s design it!

Gabriel Laskar (EPITA)

CAAL

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Processor architectureOver view

What a processor is...

A processor must be able to perform the following basic tasks: I

Execute instructions

I

Read operands

I

Store results

It needs several basic units to perform those tasks: I

A control unit

I

An arithmetic and logical unit (ALU)

I

A register bankLet"s design it!

Gabriel Laskar (EPITA)

CAAL

2015 12 / 378

Processor architectureOver view

Basic architectureControl Unit

ALUR1 R0 = 0123 = 0100 = 0023

R5R4R3R2

RegistersGabriel Laskar (EPITA)CAAL 2015 13 / 378

Processor architectureOver view

Basic architecture (2)

In this model, the system state is entirely contained in the processor. I This might be sufficient for a very basic processor I More features could be leveraged by adding registers or program stepsUnfortunately, I

Internal memory is expensive and hard to design

I

There is no communication

I Updating the program may not be easyWe need an access to memory, external devices, etc.

Gabriel Laskar (EPITA)

CAAL

2015 14 / 378

Processor architectureOver view

Basic architecture (2)

In this model, the system state is entirely contained in the processor. I This might be sufficient for a very basic processor I More features could be leveraged by adding registers or program stepsUnfortunately, I

Internal memory is expensive and hard to design

I

There is no communication

I Updating the program may not be easyWe need an access to memory, external devices, etc.

Gabriel Laskar (EPITA)

CAAL

2015 14 / 378

Processor architectureOver view

Basic architecture (2)

In this model, the system state is entirely contained in the processor. I This might be sufficient for a very basic processor I More features could be leveraged by adding registers or program stepsUnfortunately, I

Internal memory is expensive and hard to design

I

There is no communication

I Updating the program may not be easyWe need an access to memory, external devices, etc.

Gabriel Laskar (EPITA)

CAAL

2015 14 / 378

Processor architectureOver view

Revised processor model

A processor must be able to perform the following basic tasks: I Fetch instructions from an external entity and understand them (fetch anddecode) I

Execute instructions

I

Store results

to registers o rexternal memo ryIt needs several basic units to perform those tasks: I

A control unit

I

An arithmetic and logical unit (ALU)

I

A register bank

quotesdbs_dbs14.pdfusesText_20
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