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Advanced Packaging in

the new world of data

Babak Sabi

Corporate Vice President

Director of Assembly and Test Technology Development

Intel Corporation

Themes

The World Is Becoming More And More Dependent On Data Processing Ubiquitous Data Is Heavily Dependent On Advances In

System Compute & Comms

Advances In Systems Performance Require

High Bandwidth & Low Power Data Pipes Only Available On

The Age of data

BY 2020

greater computing Performance and faster, Wider data pipes required for Overall Performance

Projected Supercomputer Performance

Projected Growth in Comms Datarate

Relative Datarate

Source: https://itblog.sandisk.com/cpu-bandwidth-the-worrisome-2020-trend/Source:Top500.org

On-package Heterogeneous Integration is critical

PCB Integration

-Large Form Factor

On-Package Integration

-Lower Power -Higher Bandwidth -Heterogeneous Integration of

Multiple Nodes, Multiple IP, &

Multiple Functions

On -package vs. Off-package integration

GDDR5x

Total Capacity 4GB (1GB each)

Data rate Ÿ12Gb/s

Total BW Ÿ192 GB/s

IO Power Efficiency (Energy/bit) Ÿ(1.75 Ÿ3)X GDDR5 GDDR5 GDDR5 GDDR5 On Package Integration is More Compact, Lower Power & Higher BW (14mm x 10mm) HBM HBM

Total Capacity 4GB (1GB each)

Data rate Ÿ1 -2Gb/s

Total BW Ÿ(128-256) GB/s

IO Power Efficiency (Energy/bit) Ÿ1X

6 mm x 8 mm

note/dram/tned02_gddr5x.pdf

CPUCPU

On-PACKAGE Signaling

BW Density

(GBps/mm) 100
200
300
400
500

Complex

I/O circuits

Standard

packages

Advanced

packages with simple I/O circuits A

Advanced packaging

technologies can provide tremendous bandwidth density with affordable power consumption

Improved dielectrics

needed to enable higher data rates A B B

F. O'Mahony et al., ͞The future of

electrical IͬO for microprocessors," in Proc. IEEE Symp. VLSI Design

Automation and Test (VLSI-DAT),

Apr. 2009, pp. 31-34.

ÉÞÓÐèăâ multi-chip packaging spectrum

Organic FCXGA, FCCSP

IO/mm/lyr = 28-34

IO/mm2= 83-123

Bump Pitch = 110-90µm

IO/mm = N/A

IO/mm2= 625

Bump Pitch = 40µm

High Density Organic

Interposer

IO/mm/lyr = 100+*

IO/mm2= 331

Bump Pitch = 55µm

Si Interposer,

IO/mm/lyr = 250

IO/mm2ш331

Bump Pitchч55µm

Package Stacking

2D/2.5D (Side by Side MCPs)3D (Die &/Or Package Stacking)

3/3 L/S

PoP Pitch 0.27mm

Many Package Options Exist!!

Designers Pick the Optimal Solution for a Specific System

Die Stacking

Intel EMIB

* Oi et al. 2014 ECTC report 2m L/S, 25m pad

EMIB Provides a cost

effective, localized high density, ultra-high

Bandwidth/Low Power

Interconnect Solution

Advanced multi-chip packaging

Key FeatureScaling Metrics:

IO/mm/Layer (Escape Density)

IO/mm2(Die Area)

Package Feature Scaling Must Always keep up with Silicon Scaling

Note: IO here refers to physical bumps and wires

Directions for Heterogeneous packaging in the future

Traditional MCP

~100 Gb/s BW

State of the Art MCP

~500 Gb/s BW

1+ Tb/s BW

Die-Package Interconnect Pitch ~100m

Substrate Technology ŸAdvanced Laminate

Assembly TechnologyŸReflow CAM

Test Technology ŸArray Sort Probing

Die-Package Interconnect Pitch ~50m

Substrate Technology ŸEMIB, (Si Int + Laminate)

Assembly Technology ŸTCB

Test Technology ŸArray Sort + Self Test

Die-Package Interconnect Pitch ~10m

Substrate Technology ŸTBD

Assembly Technology ŸTBD

Test Technology ŸTBD

Industry is Challenged to Invent New Solutions for Ultra-high Density

Multi-Chip Packaging

Package technology will become more wafer

fab-like

Planarization

Pad-less Vias

Cu-Cu Bumps & Vias

Inorganic Thin Films

Achieving Interconnect Densities to Support 1+ TB/s on- Package Interconnects Will Require Novel Substrateand

Assembly Capabilities

Multi-Chip Packages will have to address other challenges

Enabling Technologies

for high Bandwidth, Off-

Package Electrical &

Optical Signaling Needed

Introduction of FIVR with package

inductors helps current demand

Improved Inductors Needed

Improved Thermal Interface

Materials (TIMs) and Interface

Control Needed for MCPs

A comprehensive test strategy needed for High Yield manufacturing

Known Good Die Test

-Binned, Stressed, Low DPM -Die, Die stacks, WLP, etc -Internal and external sourcing

Data analytics for Die to Product Targeting

-Matched Config, Speed, Power, etc. -Inventory and yield management

High Yield Packaging

-Substrate test, component test -Inline metrology -Process controlled assembly

Package Test

-Integrated test coverage -System verification -Yield recovery -DPM verification

Low Defect

Density Wafer

Fab

In conclusion

Heterogeneous On-Package Integration is a Critical Enabler for the ėÈèae ðç ËâõâĘAÒaeú âå÷âïõâèaeô

High Interconnect Density

High Bandwidth

Compact Integration of Multiple Nodes, Multiple IP, Multiple

Functions

As a community we need to focus on delivering

Increasingly High Density Interconnect

Power efficient Signaling

Efficient Power Delivery

Improved MCP Thermals

A Comprehensive Test Strategy for High Yield Manufacturingquotesdbs_dbs20.pdfusesText_26