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Reconstruction of the MOS 6502 on the Cyclone II FPGA Reconstruction of the MOS 6502 on the Cyclone II FPGA

TEAM Double O Four

Yu Chen (yc2615)

Jaebin Choi (jc3797)

Arthy Sundaram (as4304)

Anthony Erlinger (afe2104)

Reconstruction of the MOS 6502 on the Cyclone II FPGA

Table of Contents:

I. Introduction

1 Abstract

2 Preface

3 Why the 6502?

II. Understanding the Design of the 6502

1 Instruction set architecture

2 ISA Implementation

a Opcode Format b Opcode types c Addressing modes d Externally visible registers

3 Microarchitecture

a Predecode b Instruction Register c Instruction Decode d Program Counter e Address Bus Registers f Data bus g Data Output Register h Stack Pointer i Index Register j Status Register k Accumulator l ALU m Timing Control n X and Y Registers

4 Process architecture (probably not needed)

a nMOS, two phase clock design

5 Design Iterations

III. Designing our own implementation

1 Examining the ISA

2 Understanding timing diagrams

3 Understanding the addressing modes

4 Design Constraints: Latches to Flip Flops

5 Memory and IO Interface

IV. Testing

Reconstruction of the MOS 6502 on the Cyclone II FPGA

1 Divide and Conquer: Unit tests to Integration tests

2 Testing the ISA

3 Synthesis on the Cyclone II

4 Known bugs/issues

V. Application

1 Writing to the VGA Frame buffer

2 The Bouncing Ball

V. Conclusion

1 Lessons learned

2 Future direction

3 References

4 Appendix (Timing Diagrams, Adaptations)

Reconstruction of the MOS 6502 on the Cyclone II FPGA

Abstract

Owing to its low cost and simple yet powerful instruction set architecture the MOS 6502 processor is

one of the best selling processing microprocessors in history. Here we have modeled and reconstructed

a synthesizable 8-bit MOS 6502 processor in VHDL fully synthesizable on the Altera DE2 FPGA board.

In recreating the 6502 many design considerations and modifications needed to be made to the original

design in order to make it fully compatible with the more modern Cyclone II FPGA utilized on the

Altera DE2. Our design differs in the two aspects that it (1) uses only a single phase clock (as opposed

to the non-overlapping two phase clock used in the original) and (2) uses edge triggered D flip flops for

internal registers in contrast to level sensitive latches which were used in the original design. Our

design includes a basic test interface on the DE2 board in addition as well as integration test and simple

ROM programs to test functionality. The process of creating our design consisted of two major sections.

First is a thorough analysis of the architecture around the 6502 processor and the motivations behind the

original design. Secondly, we will report on the process of designing of our own 6502 from design to implementation and testing. I. Introduction: History and Significance of the 6502

Preface:

The Mos 6502 CPU has earned a prominent place in computing history. Owing to its versatility and low cost, the

6502 has been implemented in a myriad of devices including the Apple II, the Commodore 64, and the original

Nintendo Entertainment System. Along with its contemporary, the Zilog Z80, the 6502 was largely responsible for the

growth of computer games and the early operating systems in the 1980s. Today it remains in production within various

peripherals and legacy devices. However, perhaps more relevant is the This arises from the fact that the 6502 was the first CPU to instruction set with an 8 bit opcode.

Today, many consider the 6502 to be the spiritual predecessor to the multiprocessor with interlocking pipelined stages

(MIPS) CPU, which, in turn inspired the development of the ARM instruction set implemented in virtually every

mobile device.

Why the 6502?

In the concept phase of this project our group threw around many ideas. Virtually all of these were half-baked,

inconsistent, and posed a problem that was not relevant or tractable for this final project. After much discussion and

debate we narrowed down the scope of this project to focus on the hardware/software interface through the design of an

existing CPU. Again, we threw around many different ideas and after spending a great amount of time researching. We

engineered the original design from the instruction set down to the transistor. After further research it was clear that

Reconstruction of the MOS 6502 on the Cyclone II FPGA nted as the MOS 6502 processor and after a discussion with the professor, we settled on our choice on the 6502.

Before we proceed further to our implementation details, we thought it deserves to quote its history from websource

and the influence the 6502 had during its period and which inspired us to implement this processor as part of this class

project.

The 6502 processor not only brought great influences to computers market, it developed the video game console, too. Most of

the video game consoles uses refined version of 6502 processors. The first video game console which uses 6502 technology

was the Atari 2600. Atari 2600 uses a simplified version of 6502, 6507 which can only address 8KB memory. (What is the

source for this?)

II. Understanding the Design of the 6502

Instruction Set Architecture

All instructions running on the 6502 are encoded within an 8-bit space which map to unique 62 operation codes

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