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Programming the 65816

Including the 6502, 65C02 and 65802

Distributed and published under

COPYRIGHT LICENSE AND PUBLISHING AGREEMENT

with

Authors David Eyes and Ron Lichty

EFFECTIVE APRIL 28, 1992

2166 E. Brown Rd. Mesa, AZ 85213

480-962-4545 (p) 480-835-6442 (f)

www.westerndesigncenter.com

The Western Design Center

1)Chapter One..........................................................................................................12

Basic Assembly Language Programming Concepts..................................................................................12

Binary Numbers....................................................................................................................................................12

Grouping Bits into Bytes.......................................................................................................................................13

Hexadecimal Representation of Binary................................................................................................................14

The ACSII Character Set.....................................................................................................................................15

Boolean Logic........................................................................................................................................................16

Logical And........................................................................................................................................................16

Logical Or..........................................................................................................................................................17

Logical Exclusive Or...........................................................................................................................................17

Logical Complement...........................................................................................................................................17

Signed Numbers....................................................................................................................................................18

Storing Numbers in Decimal Form.......................................................................................................................19

Computer Arithmetic............................................................................................................................................20

Microprocessor Programming..............................................................................................................................20

Machine Language..............................................................................................................................................20

Assembly Language............................................................................................................................................22

Writing in Assembly Language............................................................................................................................22

Basic Programming Concepts...............................................................................................................................23

Selection Between Paths......................................................................................................................................24

2)Chapter Two..........................................................................................................26

Architecture of the 6502............................................................................................................................26

Microprocessor Architecture................................................................................................................................26

The 6502 Registers................................................................................................................................................26

The Accumulator................................................................................................................................................27

The X and Y Index Registers...............................................................................................................................29

The Status Register.............................................................................................................................................29

The Stack Pointer................................................................................................................................................31

The Program Counter..........................................................................................................................................33

Addressing Modes.................................................................................................................................................33

The 6502 System Design........................................................................................................................................38

Memory Order of Multiple-Byte Values..............................................................................................................39

Memory-Mapped Input/Output............................................................................................................................39

NMOS Process......................................................................................................................................................40

Bugs and Quirks...................................................................................................................................................40

3)Chapter Three.......................................................................................................41

Architecture of the 65C02.........................................................................................................................41

The 65C02 Architecture........................................................................................................................................41

Addressing Modes.................................................................................................................................................41

CMOS Process......................................................................................................................................................42

Bugs and Quirks...................................................................................................................................................42

4)Chapter Four.........................................................................................................44

Sixteen-Bit Architecture The 65816 and the 65802...................................................................................44

The Western Design Center

Power-On Status: 6502 Emulation Mode..................................................................................................45

The Full-Featured 65x Processor: The 65816 in Native Mode................................................................45

The Program Bank Register.................................................................................................................................47

The Data Bank Register........................................................................................................................................48

The Direct Page Register......................................................................................................................................48

The Stack Pointer..................................................................................................................................................48

Accumulator and Index Registers........................................................................................................................48

Switching Registers Between Eight and Sixteen Bits............................................................................................50

The Status Register...............................................................................................................................................50

6502/65C02 Addressing Modes on the 65816........................................................................................................51

New 65816 Addressing Modes..............................................................................................................................52

The 65802 Native Mode.............................................................................................................................55

Emulation Mode....................................................................................................................................................58

Emulation Mode Registers....................................................................................................................................60

Switching Between 6502 Emulation and Native Modes............................................................................61

Switching from Emulation to Native Mode..........................................................................................................61

Switching from Native to Emulation Mode..........................................................................................................61

65802/65816 Bugs and Quirks...................................................................................................................62

5)Chapter Five..........................................................................................................64

SEP, REP, and Other Details....................................................................................................................64

The Assembler Used in This Book........................................................................................................................66

Address Notation...................................................................................................................................................68

6)Chapter Six............................................................................................................69

First Examples: Moving Data....................................................................................................................69

Loading and Storing Registers.............................................................................................................................71

Effect of Load and Store Operations on Status Flags............................................................................................73

Moving Data Using the Stack..............................................................................................................................73

Pushing the Basic 65x Registers..........................................................................................................................76

Pulling the Basic 65x Registers...........................................................................................................................76

Pushing and Pulling the 65816's Additional Registers..........................................................................................78

Pushing Effective Addresses................................................................................................................................79

Other Attributes of Push and Pull........................................................................................................................79

Moving Data Between Registers...........................................................................................................................79

Storing Zero to Memory.......................................................................................................................................86

Block Moves..........................................................................................................................................................87

7)Chapter Seven.......................................................................................................89

SimpleAddressing Modes..........................................................................................................................89

Immediate Addressing..........................................................................................................................................90

Absolute Addressing.............................................................................................................................................92

Direct Page Addressing.........................................................................................................................................94

Absolute Indexed with X and Absolute Indexed with Y Addressing...................................................................98

Direct Page Indexed with X and Direct Page Indexed with Y Addressing........................................................101

Accumulator Addressing....................................................................................................................................103

Implied Addressing.............................................................................................................................................103

Direct Page Indirect Addressing.........................................................................................................................104

Absolute Long Addressing..................................................................................................................................105

The Western Design Center

Absolute Long Indexed with X Addressing........................................................................................................108

Direct Page Indirect Long...................................................................................................................................109

Block Move..........................................................................................................................................................110

8)Chapter Eight......................................................................................................111

The Flow of Control.................................................................................................................................111

Jump Instructions...............................................................................................................................................112

Conditional Branching........................................................................................................................................114

Branching Based on the Zero Flag.....................................................................................................................115

Branching Based on the Carry Flag...................................................................................................................117

Branching Based on the Negative Flag..............................................................................................................118

Branching Based on the Overflow Flag..............................................................................................................119

Limitations of Conditional Branches..................................................................................................................119

Unconditional Branching....................................................................................................................................119

9)Chapter Nine.......................................................................................................122

Built-In Arithmetic Functions.................................................................................................................122

Increment and Decrement..................................................................................................................................123

Addition and Subtraction: Unsigned Arithmetic..............................................................................................127

Signed Arithmetic...............................................................................................................................................134

Signed Comparisons............................................................................................................................................136

Decimal Mode.....................................................................................................................................................137

10)Chapter Ten......................................................................................................139

Logic and Bit Manipulation Operations.................................................................................................139

Logic Functions...................................................................................................................................................139

Logical AND....................................................................................................................................................140

Logical OR.......................................................................................................................................................142

Logical Exclusive-Or........................................................................................................................................143

Bit Manipulation.................................................................................................................................................145

Shifts and Rotates...............................................................................................................................................146

11)Chapter Eleven.................................................................................................154

The Complex Addressing Modes.............................................................................................................154

Relocating the Direct Page..................................................................................................................................155

Assembler Addressing Mode Assumptions.........................................................................................................156

Direct Page Indirect Indexed With Y Addressing..............................................................................................158

Direct Page Indexing Indirect Addressing.........................................................................................................161

Absolute Indexed Indirect Addressing...............................................................................................................163

Direct Page Indirect Long Indexed with Y Addressing......................................................................................165

Stack Relative Addressing..................................................................................................................................166

Stack Relative Indirect Indexed Addressing......................................................................................................168

Push Effective Instructions.................................................................................................................................169

12)Chapter Twelve.................................................................................................174

The Basic Building Block:.......................................................................................................................174

The Subroutine....................................................................................................................................................174

The Jump-To-Subroutine Instruction................................................................................................................175

The Return-from-Subroutine Instruction..........................................................................................................175

JRS Using Absolute Indexed Indirect Addressing.............................................................................................177

The Long Jump to Subroutine............................................................................................................................178

Return from Subroutine Long............................................................................................................................178

Branch to Subroutine..........................................................................................................................................179

Coding a Subroutine: How and When................................................................................................................180

6502 Eight-Bit Negation - A Library Example..................................................................................................180

65C02, 65802, and 65816 Eight-Bit Negation....................................................................................................181

The Western Design Center

6502 Sixteen-Bit Negation................................................................................................................................181

65802 and 65816 Sixteen-Bit Negation..............................................................................................................181

Parameter Passing..............................................................................................................................................182

13)Chapter Thirteen..............................................................................................192

Interrupts and System Control Instructions...........................................................................................192

Processing Interrupts.........................................................................................................................................197

Interrupt Response Time...................................................................................................................................200

Status Register Control Instruction....................................................................................................................201

No Operation Instructions..................................................................................................................................202

14)Chapter Fourteen.............................................................................................204

Selected Code Samples.............................................................................................................................204

6502 Multiplication...........................................................................................................................................205

65C02 Multiplication........................................................................................................................................205

65802 and 65816 Multiplication........................................................................................................................205

6502 Division...................................................................................................................................................209

65C02 Division.................................................................................................................................................211

65802/65816 Division.......................................................................................................................................211

Calling an Arbitrary 6502 Routine.....................................................................................................................213

Testing Processor Type.......................................................................................................................................219

Compiler-Generated 65816 Code for a RecursiveProgram...............................................................................220

The Same Example Hand-Coded in Assembly Language...................................................................................224

The Sieve of Eratosthenes Benchmark...............................................................................................................226

15)Chapter Fifteen................................................................................................230

DEGUG16 - A 65816 Programming Tool...............................................................................................230

16)Chapter Sixteen................................................................................................276

Design and Debugging.............................................................................................................................276

Debugging Checklist...........................................................................................................................................276

Decimal Flag....................................................................................................................................................276

Adjusting Carry Prior to Add / Subtract.............................................................................................................276

65x Left-to-Right Syntax...................................................................................................................................276

65x Branches....................................................................................................................................................277

6502 Jump Bug.................................................................................................................................................277

Interrupt-Handling Code....................................................................................................................................277

65802/65816: Emulation Versus Native Mode...................................................................................................277

65802/65816: Eight-Bit Versus Sixteen-Bit Registers........................................................................................278

65802/65816: The Direct Page..........................................................................................................................278

The Western Design Center

65802/65816: Stack Overruns Program or Data.................................................................................................278

65802/65816: JSR/JSL and RTS/RTL................................................................................................................278

65802/65816: MVN/MVP.................................................................................................................................278

Return Address.................................................................................................................................................279

Inconsistent Assembler Syntax..........................................................................................................................279

Generic Bugs: They Can Happen Anywhere......................................................................................................279

Uninitialized Variables......................................................................................................................................279

Missing Code....................................................................................................................................................279

Failure to Increment the Index in a Loop............................................................................................................279

Failure to Clean Up Stack..................................................................................................................................280

Immediate Data Versus Memory Location.........................................................................................................280

Initializing the Stack Pointer from a Subroutine.................................................................................................280

Top-Down Design and Structured Programming..............................................................................................280

17)Chapter Seventeen............................................................................................283

The Addressing Modes............................................................................................................................283

Absolute Addressing.........................................................................................................................................288

Absolute Indexed, X Addressing.......................................................................................................................289

Absolute Indexed, Y Addressing.......................................................................................................................290

Absolute Indexed Indirect Addressing...............................................................................................................291

Absolute Indirect Addressing............................................................................................................................292

Absolute Indirect Long Addressing...................................................................................................................293

JMP [addr]........................................................................................................................................................293

Absolute Long Addressing................................................................................................................................294

Absolute Long Indexed, X Addressing..............................................................................................................295

Accumulator Addressing...................................................................................................................................296

Block Move Addressing....................................................................................................................................297

Direct Page Addressing.....................................................................................................................................298

Direct Page Indexed, X Addressing...................................................................................................................299

Direct Page Indexed, Y Addressing...................................................................................................................300

Direct Page Indexed Indirect, X Addressing.......................................................................................................301

Direct Page Indirect Addressing........................................................................................................................302

Direct Page Indirect Long Addressing...............................................................................................................303

Direct Page Indirect Indexed, Y Addressing.......................................................................................................304

Direct Page Indirect Long Indexed, Y Addressing..............................................................................................305

Immediate Addressing.......................................................................................................................................306

Implied Addressing...........................................................................................................................................307

Program Counter Relative Addressing...............................................................................................................308

Program Counter Relative Long Address...........................................................................................................309

Stack (Absolute) Addressing.............................................................................................................................310

Stack (Direct Page Indirect) Addressing............................................................................................................312

Stack (Interrupt) Addressing..............................................................................................................................314

Stack (Program Counter Relative) Addressing...................................................................................................316

Stack (Pull) Addressing.....................................................................................................................................317

Stack (Push) Addressing....................................................................................................................................319

Stack (RTI) Addressing.....................................................................................................................................321

Stack (RTL) Addressing....................................................................................................................................322

Stack (RTS) Addressing....................................................................................................................................323

Stack Relative Addressing.................................................................................................................................324

Stack Relative Indirect Indexed, Y Addressing..................................................................................................325

18)Chapter Eighteen..............................................................................................326

The Instruction Sets.................................................................................................................................326

Add With Carry..................................................................................................................................................327

And Accumulator with Memory.........................................................................................................................328

The Western Design Center

Shift Memory or Accumulator Left....................................................................................................................329

Branch if Carry Clear.........................................................................................................................................330

Branch if Carry Set.............................................................................................................................................331

Branch if Equal...................................................................................................................................................332

Test Memory Bits against Accumulator.............................................................................................................333

Branch if Minus..................................................................................................................................................334

Branch if Not Equal............................................................................................................................................335

Branch if Plus......................................................................................................................................................336

Branch Always....................................................................................................................................................337

Software Break...................................................................................................................................................338

Branch Always Long...........................................................................................................................................340

Branch if Overflow Clear...................................................................................................................................341

Branch if Overflow Set.......................................................................................................................................342

Clear Carry Flag.................................................................................................................................................343

Clear Decimal Mode Flag...................................................................................................................................344

Clear Interrupt Disable Flag..............................................................................................................................345

Clear Overflow Flag............................................................................................................................................346

Compare Accumulator with Memory.................................................................................................................347

Co-Processor Enable...........................................................................................................................................349

Compare Index Register X with Memory...........................................................................................................350

Compare Index Register Y with Memory CPY..................................................................................................351

Decrement Index Register X...............................................................................................................................353

Decrement Index Register Y...............................................................................................................................354

Exclusive-OR Accumulator with Memory.........................................................................................................355

Increment Index Register X................................................................................................................................358

Increment Index Register Y................................................................................................................................359

Jump to Subroutine Long (Inter-Bank).............................................................................................................361

Jump to Subroutine.............................................................................................................................................362

Load Accumulator from Memory.......................................................................................................................363

Load Index Register X from Memory................................................................................................................364

Load Index Register Y from Memory................................................................................................................365

Logical Shift Memory or Accumulator Right.....................................................................................................366

Block Move Next.................................................................................................................................................367

Block Move Previous...........................................................................................................................................368

No Operation.......................................................................................................................................................369

OR Accumulator with Memory..........................................................................................................................370

Push Effective Absolute Address........................................................................................................................372

Push Effective Indirect Address.........................................................................................................................373

Push Effective PC Relative Indirect Address.....................................................................................................374

Push Accumulator...............................................................................................................................................375

Push Data Bank Register....................................................................................................................................376

Push Direct Page Register...................................................................................................................................377

Push Program Bank Register.............................................................................................................................378

Push Processor Status Register...........................................................................................................................379

Push Index Register............................................................................................................................................380

Push Index Register............................................................................................................................................381

Pull Accumulator................................................................................................................................................382

Pull Data Bank Register......................................................................................................................................383

Pull Direct Page Register....................................................................................................................................384

Pull Status Flags..................................................................................................................................................385

Pull Index Register X from Stack.......................................................................................................................386

Pull Index Register Y from Stack.......................................................................................................................387

Reset Status Bits..................................................................................................................................................388

Rotate Memory or Accumulator Left.................................................................................................................389

The Western Design Center

Rotate Memory or Accumulator Right...............................................................................................................390

Return from Interrupt........................................................................................................................................391

Return from Subroutine Long............................................................................................................................393

Return from Subroutine.....................................................................................................................................394

Subtract with Borrow from Accumulator..........................................................................................................395

Set Carry Flag.....................................................................................................................................................397

Set Decimal Mode Flag.......................................................................................................................................398

Set Interrupt Disable Flag..................................................................................................................................399

Set Status Bits.....................................................................................................................................................400

Store Accumulator to Memory...........................................................................................................................401

Stop the Processor...............................................................................................................................................402

Store Index Register X to Memory.....................................................................................................................403

Store Index Register Y to Memory.....................................................................................................................404

Store Zero to Memory.........................................................................................................................................405

Transfer Accumulator to Index Register X........................................................................................................406

Transfer Accumulator to Index Register Y........................................................................................................407

Transfer 16-Bit Accumulator to Direct Page Register.......................................................................................408

Transfer Accumulator to Stack Pointer.............................................................................................................409

Transfer Direct Page Register to 16-Bit Accumulator.......................................................................................410

Test and Reset Memory Bits Against Accumulator............................................................................................411

Test and Set Memory Bits Against Accumulator...............................................................................................412

Transfer Stack Pointer to 16-Bit Accumulator...................................................................................................413

Transfer Stack Pointer to Index Register X.......................................................................................................414

Transfer Index Register X to Accumulator........................................................................................................415

Transfer Index Register X to Stack Pointer.......................................................................................................416

Transfer Index Register X to Y..........................................................................................................................417

Transfer Index Register Y to Accumulator........................................................................................................418

Transfer Index register Y to X............................................................................................................................419

Wait for Interrupt...............................................................................................................................................420

Reserved for Future Expansion..........................................................................................................................421

Exchange the B and A Accumulators.................................................................................................................422

Exchange Carry and Emulation Bits..................................................................................................................423

19)Chapter Nineteen..............................................................................................424

Instruction Lists.......................................................................................................................................424

Addressing mode box:.......................................................................................................................................434

Operation column:............................................................................................................................................434

Bytes, cycles, and status codes:..........................................................................................................................435

Op Code Matrix Legend.....................................................................................................................................437

Table of Figures

FIGURE 1-1 BINARY REPRESENTATION.............................................................................................................................13

FIGURE 1-2 BIT NUMBERS...............................................................................................................................................14

FIGURE 1-3 ANDING BITS...............................................................................................................................................16

FIGURE 1-4 ORING BITS..................................................................................................................................................17

FIGURE 1-5 EXCLUSIVE ORING BITS............................................................................................................................17

FIGURE 1-6 COMPLEMENTING BITS.............................................................................................................................18

FIGURE 1-7 COMPLEMENTING BITS USING EXCLUSIVE OR..........................................................................................18

FIGURE 1-8 MULTIPLE-PRECISION ARITHMETIC...............................................................................................................21

FIGURE 1-9 TYPICAL ASSEMBLER SOURCE CODE.............................................................................................................23

FIGURE 2-1 6502 PROGRAMMING MODEL........................................................................................................................28

FIGURE 2-2 INITIALIZING THE STACK POINTER TO $FF.....................................................................................................32

FIGURE 2-3 AFTER PUSHING THE ACCUMULATOR.............................................................................................................33

FIGURE 2-4 INDEXING: BASE PLUS INDEX........................................................................................................................35

FIGURE 2-5 INDIRECTION: OPERAND LOCATES INDIRECT ADDRESS..................................................................................36

FIGURE 4-1 65816 NATIVE MODE PROGRAMMING MODEL..............................................................................................46

FIGURE 4-2 RESULTS OF SWITCHING REGISTER SIZE........................................................................................................51

The Western Design Center

FIGURE 4-3 65802 NATIVE MODE PROGRAMMING MODEL..............................................................................................57

FIGURE 4-4 65816 EMULATION MODE PROGRAMMING MODEL........................................................................................60

FIGURE 6-1 STACK MEMORY..........................................................................................................................................75

FIGURE 6-2. PUSH..........................................................................................................................................................77

FIGURE 6-3 REGISTER TRANSFERS BETWEEN DIFFERENT-SIZED REGISTERS.....................................................................83

FIGURE 7-1 IMMEDIATE ADDRESSING: 8 VS. 16 BITS......................................................................................................91

FIGURE 7-2 ABSOLUTE ADDRESSING...............................................................................................................................93

FIGURE 7-3 ZERO PAGE ADDRESSING..............................................................................................................................94

FIGURE 7-4 INDEXING....................................................................................................................................................97

FIGURE 7-5 INDEXING BEYOND THE END OF THE BANK...................................................................................................98

FIGURE 7-6 ABSOLUTE INDEXING WITH A GENERIC INDEX REGISTER.............................................................................100

FIGURE 7-7 DIRECT PAGE INDEXING WITH A GENERIC INDEX REGISTER.........................................................................102

FIGURE 7-8 DIRECT PAGE INDIRECT ADDRESSING.........................................................................................................105

FIGURE 7-9 ABSOLUTE LONG ADDRESSING...................................................................................................................108

FIGURE 7-10 DIRECT PAGE INDIRECT LONG ADDRESSING..............................................................................................110

FIGURE 8-1 JUMP'S ABSOLUTE INDIRECT ADDRESSING MODE.......................................................................................113

FIGURE 8-2. RELATIVE BRANCH CALCULATION............................................................................................................115

FIGURE 8-3. LINKED LIST.............................................................................................................................................117

FIGURE 10-1 THE AND OPERATION..............................................................................................................................140

FIGURE 10-2 SHIFT AND ROTATE LEFT..........................................................................................................................148

FIGURE 10-3 SHIFT AND ROTATE RIGHT........................................................................................................................149

FIGURE 11-1 POSTINDEXING.........................................................................................................................................159

FIGURE 11-2 PREINDEXING...........................................................................................................................................162

FIGURE 11-3 ABSOLUTE INDEXED INDIRECT..................................................................................................................165

FIGURE 11-4 POSTINDEXED LONG.................................................................................................................................167

FIGURE 11-5 STACK RELATIVE.....................................................................................................................................168

FIGURE 11-6 STACK RELATIVE INDIRECT INDEXED........................................................................................................169

FIGURE 11-7 PEA ADDRESSING....................................................................................................................................170

FIGURE 11-8 PEI ADDRESSING.....................................................................................................................................171

FIGURE 11-9. PER ADDRESSING...................................................................................................................................172

FIGURE 12-1 JSR.........................................................................................................................................................176

FIGURE 12-2 RTS.........................................................................................................................................................177

FIGURE 12-3 JSL..........................................................................................................................................................178

FIGURE 12-4 RTL........................................................................................................................................................179

FIGURE 13-1 I/O MANAGEMENT: INTERRUPTS VS. POLLING..........................................................................................193

FIGURE 13-2 INTERRUPT PROCESSING...........................................................................................................................194

FIGURE 13-3BREAK SIGNATURE BYTE ILLUSTRATION....................................................................................................197

FIGURE 13-4 6522 VIA INTERRUPT FLAG REGISTER......................................................................................................198

FIGURE 14-1 STACK SNAPSHOT AFTER PEI (12) INSTRUCTION.......................................................................................218

FIGURE 15-1 DISASSEMBLY OUTPUT.............................................................................................................................231

FIGURE 15-2 TRACER OUTPUT......................................................................................................................................231

FIGURE 17-1 6502/65C02 PROGRAMMING MODEL........................................................................................................284

FIGURE 17-2. 65802 NATIVE MODE PROGRAMMING MODEL..........................................................................................285

FIGURE 17-3 65816 NATIVE MODE PROGRAMMING MODEL...........................................................................................286

FIGURE 17-4 65816 EMULATION MODE PROGRAMMING MODEL....................................................................................287

FIGURE 18-1 AND TRUTH TABLE.................................................................................................................................328

FIGURE 18-2 ASL........................................................................................................................................................329

FIGURE 18-3 65802/65816 STACK AFTER BRK.............................................................................................................339

FIGURE 18-4 STACK AFTER COP...................................................................................................................................349

FIGURE 18-5EXCLUSIVE OR TRUTH TABLE....................................................................................................................355

FIGURE 18-6 LSR.........................................................................................................................................................366

FIGURE 18-7 LOGICAL OR TRUTH TABLE.....................................................................................................................370

FIGURE 18-8 ROL........................................................................................................................................................389

FIGURE 18-9 ROR........................................................................................................................................................390

FIGURE 18-10NATIVE MODE STACK BEFORE RTI...........................................................................................................391

FIGURE 18-11 STACK BEFORE RTL...............................................................................................................................393

FIGURE 18-12 STACK BEFORE RTS...............................................................................................................................394

The Western Design Center

Table of Tables

TABLE 1-1 DECIMAL AND HEX NUMBERS........................................................................................................................15

TABLE 1-2 TRUTH TABLE FOR AND...............................................................................................................................17

TABLE 1-3 TRUTH TABLE FOR OR...................................................................................................................................17

TABLE 1-4 TRUTH TABLE FOR EXCLUSIVE OR.............................................................................................................17

TABLE 1-5 TRUTH TABLE FOR COMPLEMENT..............................................................................................................18

TABLE 1-6 THE EIGHT-BIT RANGE OF TWO'S-COMPLEMENT NUMBERS............................................................................19

TABLE 1-7 THE FIRST 16 BCD NUMBERS........................................................................................................................20

TABLE 2-1 STATUS REGISTER CONDITION CODE FLAGS....................................................................................................30quotesdbs_dbs11.pdfusesText_17

[PDF] [PDF] Programming the 65816 - 6502org