[PDF] [PDF] COUNTERS AND TIME DELAYS

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[PDF] COUNTERS AND TIME DELAYS

TIME DELAY USING A REGISTER PAIR Label Opcode Operand Comments T states LXI B,2384H Load BC with 16-bit count 10 LOOP: DCX B Decrement 

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COUNTERS AND TIME

DELAYS

LECTURE 3

A counter is designed simply by loading appropriate number into one of the registers and using INR or

DNR instructions.

Loop is established to update the count.

Each count is checked to determine whether it has reached final number ;if not, the loop is repeated.

COUNTER AND TIME DELAYS

TIME DELAY

Procedure used to design a specific delay.

A register is loaded with a number , depending on the time delay required and then the register is

decremented until it reaches zero by setting up a loop with conditional jump instruction.

Time delay using

One register:

LABEL OPCODE OPERAND COMMENTS T

STATES

MVI C,FFH ;Load register C 7 DCR C ;Decrement C 4 JNZ LOOP ;Jump back to 10/7 decrement C

Clock frequency of the system = 2 MHz

Clock period= 1/T= 0.5 s

Time to execute MVI = 7 T states * 0.5= 3.5 s

Time Delay in Loop TL= T*Loop T states * N10

= 0.5 * 14* 255 = 1785 s = 1.8 ms N10 = Equivalent decimal number of hexadecimal count loaded in the delay register

TLA= Time to execute loop instructions

=TL (3T states* clock period)=1785-1.5=1783.5 s LOOP:

TIME DELAY USING A REGISTER PAIR

Label Opcode Operand Comments T states LXI B,2384H Load BC with 16-bit count 10

LOOP: DCX B Decrement BC by 1 6

MOV A,C Place contents of C in A 4 ORA B OR B with C to set Zero flag 4 JNZ LOOP if result not equal to 0 , 10/7 jump back to loop

Time Delay in Loop TL= T*Loop T states * N10

= 0.5 * 24* 9092 = 109 ms

Time Delay using a LOOP within a LOOP

MVI B,38H 7T Delay in Loop TL1=1783.5 s LOOP2: MVI C,FFH 7T Delay in Loop TL2= (0.5*21+TL1)*56

LOOP1: DCR C 4T =100.46ms

JNZ LOOP1 10/7 T

DCR B 4T

JNZ LOOP 2 10/7T

Flowchart

for time delay with two loops

Flowchart of a counter with time delay

ILLUSTRATIVE PROGRAM: HEXADECIMAL

COUNTER

Write a Program to count continuously from FFH to 00H using register C with delay count 8CH between each count and

display the number at one of the output ports.

MVI B,00H

NEXT: DCR B

MVI C,8CH

DELAY: DCR C

JNZ DELAY

MOV A,B

OUT PORT#

JMP NEXT

ILLUSTRATIVE PROGRAM: ZERO TO NINE

(M

ODULO TEN) COUNTER

START: MVI B,00H

MOV A,B

DSPLAY: OUT PORT #

LXI H,16-bit

LOOP: DCX H

MOV A,L

ORA H

JNZ LOOP

INR B

MOV A,B

CPI 0AH

JNZ DSPLAY

JZ START

Start

Initialize counter

Display Output

Load Delay register

Decrement Delay register

Is Delay register=0?

Next Count

Is count =0AH?

If yes, Initialize counter

If no, Display Output

ILLUSTRATIVE PROGRAM:

GENERATING PULSE WAVEFORMS

Generates a continuous

square wave with the period of 500 Micro Sec. Assume the system clock period is

325ns, and use bit D0

output the square wave.

Delay outside loop: T0=46

T states * 325=14.95 micro

sec.

Loop delay: TL=4.5 micro

sec

Total Td=To+TL

Count=34 H

DEBUGGING COUNTER AND

TIME

DELAY PROGRAMS

It is designed to count

from 100(base 10) to 0 in Hex continuously with a 1 second delay between each count.

The delay is set up

using two loops. The inner loop is executed to provide approximately

100ms delay and is

repeated 10 times, using outer loop to provide a total delay of 1 second.

The clock period of

system is 330ns.quotesdbs_dbs3.pdfusesText_6