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ARM v7-M Architecture

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ARMv7-M Architecture Reference Manual

Preface

About this manual .............................................................................. xviii

Using this manual ............................................................................... xix

Conventions ....................................................................................... xxii

Further reading .................................................................................. xxiii

Feedback .......................................................................................... xxiv

Part A Application Level Architecture

Chapter A1 Introduction

A1.1 The ARM Architecture profile .................................................... A1-2

Chapter A2 Application Level Programmers' Model

A2.1 About the Application level programmers' model ............................. A2-2 A2.2 ARM core data types and arithmetic ................................................ A2-3 A2.3 Registers and execution state ........................................................ A2-11 A2.4 Exceptions, faults and interrupts .................................................... A2-15

A2.5 Coprocessor support ...................................................................... A2-16

Chapter A3 ARM Architecture Memory Model

A3.1 Address space ................................................................................. A3-2

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A3.2 Alignment support ............................................................................ A3-3

A3.3 Endian support ................................................................................. A3-5

A3.4 Synchronization and semaphores .................................................... A3-8 A3.5 Memory types and attributes and the memory order model .......... A3-18

A3.6 Access rights .................................................................................. A3-28

A3.7 Memory access order .................................................................... A3-30 A3.8 Caches and memory hierarchy ...................................................... A3-38

Chapter A4 The ARMv7-M Instruction Set

A4.1 About the instruction set .................................................................. A4-2

A4.2 Unified Assembler Language ........................................................... A4-4

A4.3 Branch instructions .......................................................................... A4-7

A4.4 Data-processing instructions ............................................................ A4-8 A4.5 Status register access instructions ................................................ A4-15 A4.6 Load and store instructions ............................................................ A4-16 A4.7 Load/store multiple instructions ..................................................... A4-19 A4.8 Miscellaneous instructions ............................................................. A4-20 A4.9 Exception-generating instructions .................................................. A4-21

A4.10 Coprocessor instructions ............................................................... A4-22

Chapter A5 Thumb Instruction Set Encoding

A5.1 Thumb instruction set encoding ....................................................... A5-2 A5.2 16-bit Thumb instruction encoding ................................................... A5-5 A5.3 32-bit Thumb instruction encoding ................................................. A5-13

Chapter A6 Thumb Instruction Details

A6.1 Format of instruction descriptions .................................................... A6-2 A6.2 Standard assembler syntax fields .................................................... A6-7

A6.3 Conditional execution ....................................................................... A6-8

A6.4 Shifts applied to a register ............................................................. A6-12

A6.5 Memory accesses .......................................................................... A6-15

A6.6 Hint Instructions ............................................................................. A6-16

A6.7 Alphabetical list of ARMv7-M Thumb instructions .......................... A6-17

Part B System Level Architecture

Chapter B1 System Level Programmers' Model

B1.1 Introduction to the system level ....................................................... B1-2 B1.2 ARMv7-M: a memory mapped architecture ..................................... B1-3 B1.3 System level operation and terminology overview ........................... B1-4

B1.4 Registers .......................................................................................... B1-8

B1.5 Exception model ............................................................................ B1-14

Chapter B2 System Memory Model

B2.1 Introduction ...................................................................................... B2-2

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B2.2 Pseudocode details of general memory system operations ............. B2-3

Chapter B3 System Address Map

B3.1 The system address map ................................................................. B3-2 B3.2 System Control Space (SCS) ........................................................... B3-6

B3.3 System timer - SysTick .................................................................. B3-24

B3.4 Nested Vectored Interrupt Controller (NVIC) ................................. B3-28 B3.5 Protected Memory System Architecture (PMSAv7) ....................... B3-35

Chapter B4 ARMv7-M System Instructions

B4.1 Alphabetical list of ARMv7-M system instructions ............................ B4-2

Part C Debug Architecture

Chapter C1 ARMv7-M Debug

C1.1 Introduction to debug ....................................................................... C1-2

C1.2 The Debug Access Port (DAP) ........................................................ C1-4 C1.3 Overview of the ARMv7-M debug features ...................................... C1-8

C1.4 Debug and reset ............................................................................ C1-13

C1.5 Debug event behavior .................................................................... C1-14 C1.6 Debug register support in the SCS ................................................ C1-19 C1.7 Instrumentation Trace Macrocell (ITM) support ............................. C1-27 C1.8 Data Watchpoint and Trace (DWT) support ................................... C1-33 C1.9 Embedded Trace (ETM) support .................................................... C1-56 C1.10 Trace Port Interface Unit (TPIU) .................................................... C1-57 C1.11 Flash Patch and Breakpoint (FPB) support .................................... C1-61

Appendix A CPUID

A.1 Core Feature ID Registers ......................................................... AppxA-2 A.2 Processor Feature register0 (ID_PFR0) .................................... AppxA-4 A.3 Processor Feature register1 (ID_PFR1) .................................... AppxA-5 A.4 Debug Features register0 (ID_DFR0) ........................................ AppxA-6 A.5 Auxiliary Features register0 (ID_AFR0) ..................................... AppxA-7 A.6 Memory Model Feature registers ............................................... AppxA-8 A.7 Instruction Set Attribute registers - background information ... AppxA-10 A.8 Instruction Set Attribute registers - details ............................... AppxA-12

Appendix B ARMv7-M infrastructure IDs

Appendix C Legacy Instruction Mnemonics

C.1 Thumb instruction mnemonics ................................................... AppxC-2 C.2 Pre-UAL pseudo-instruction NOP .............................................. AppxC-6

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Appendix D Deprecated Features in ARMv7-M

Appendix E Debug ITM and DWT packet protocol

E.1 Packet Types ............................................................................. AppxE-2

E.2 DWT packet formats .................................................................. AppxE-8

Appendix F ARMv7-R differences

F.1 Endian support ........................................................................... AppxF-2

F.2 Application level support ............................................................ AppxF-3 F.3 System level support .................................................................. AppxF-4

F.4 Debug support ........................................................................... AppxF-5

Appendix G Pseudocode definition

G.1 Instruction encoding diagrams and pseudocode ...................... AppxG-2 G.2 Limitations of pseudocode ........................................................ AppxG-4

G.3 Data Types ................................................................................ AppxG-5

G.4 Expressions .............................................................................. AppxG-9

G.5 Operators and built-in functions .............................................. AppxG-11 G.6 Statements and program structure ......................................... AppxG-17 G.7 Miscellaneous helper procedures and functions ..................... AppxG-22

Appendix H Pseudocode Index

H.1 Pseudocode operators and keywords ........................................ AppxH-2 H.2 Pseudocode functions and procedures ...................................... AppxH-5

Appendix I Register Index

I.1 ARM core registers ..................................................................... AppxI-2

I.2 Memory mapped system registers .............................................. AppxI-3

I.3 Memory mapped debug registers ...........

.................................... AppxI-5

Glossary

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List of Tables

ARMv7-M Architecture Reference Manual

Change History .................................................................................................... ii

Table A3-1 Little-endian byte format ................................................................................. A3-5

Table A3-2 Big-endian byte format ................................................................................... A3-5

Table A3-3 Little-endian memory system ......................................................................... A3-6

Table A3-4 Big-endian memory system ............................................................................ A3-6

Table A3-5 Load-store and element size association ....................................................... A3-7

Table A3-6 Effect of Exclusive instructions and write operations on local monitor ......... A3-10 Table A3-7 Effect of load/store operations on global monitor for processor(n) ............... A3-14

Table A3-8 Memory attribute summary .......................................................................... A3-19

Table A4-1 Branch instructions ......................................................................................... A4-7

Table A4-2 Standard data-processing instructions ........................................................... A4-9

Table A4-3 Shift instructions ........................................................................................... A4-10

Table A4-4 General multiply instructions ........................................................................ A4-11

Table A4-5 Signed multiply instructions .......................................................................... A4-11

Table A4-6 Unsigned multiply instructions ...................................................................... A4-11

Table A4-7 Core saturating instructions ......................................................................... A4-12

Table A4-8 Packing and unpacking instructions ............................................................. A4-13

Table A4-9 Miscellaneous data-processing instructions ................................................. A4-14

Table A4-10 Load and store instructions .......................................................................... A4-16

Table A4-11 Load/store multiple instructions .................................................................... A4-19

Table A4-12 Miscellaneous instructions ........................................................................... A4-20

Table A5-1 16-bit Thumb instruction encoding ................................................................. A5-5

Table A5-2 16-bit shift(immediate), add, subtract, move and compare encoding ............. A5-6

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Table A5-3 16-bit data processing instructions ................................................................. A5-7

Table A5-4 Special data instructions and branch and exchange ...................................... A5-8

Table A5-5 16-bit Load/store instructions ......................................................................... A5-9

Table A5-6 Miscellaneous 16-bit instructions ................................................................. A5-10

Table A5-7 If-Then and hint instructions ............ ............................................................. A5-11

Table A5-8 Branch and supervisor call instructions ........................................................ A5-12

Table A5-9 32-bit Thumb encoding ................................................................................ A5-13

Table A5-10 32-bit modified immediate data processing instructions .............................. A5-14

Table A5-11 Encoding of modified immediates in Thumb data-processing instructions .. A5-15

Table A5-12 32-bit unmodified immediate data processing instructions .......................... A5-17

Table A5-13 Branches and miscellaneous control instructions ........................................ A5-18

Table A5-14 Change Processor State, and hint instructions ............................................ A5-19

Table A5-15 Miscellaneous control instructions ............................................................... A5-19

Table A5-16 Load/store multiple instructions .................................................................... A5-20

Table A5-17 Load/store dual or exclusive, table branch ................................................... A5-21

Table A5-18 Load word .................................................................................................... A5-22

Table A5-19 Load halfword ............................................................................................... A5-23

Table A5-20 Load byte, preload ....................................................................................... A5-24

Table A5-21 Store single data item .................................................................................. A5-25

Table A5-22 Data-processing (shifted register) ................................................................ A5-26

Table A5-23 Move register and immediate shifts ............................................................. A5-27

Table A5-24 Data processing (register) ............................................................................ A5-28

Table A5-25 Miscellaneous operations ............................................................................. A5-29

Table A5-26 Multiply, and multiply accumulate operations ............................................... A5-30

Table A5-27 Long multiply, long multiply accumulate, and divide operations .................. A5-31

Table A5-28 Coprocessor instructions .............................................................................. A5-32

Table A6-1 Condition codes ............................................................................................. A6-8

Table A6-2 Effect of IT execution state bits .................................................................... A6-11

Table A6-3 Determination of mask field ......................................................................... A6-79

Table A6-4 MOV (shift, register shift) equivalences) .................................................... A6-152

Table B1-1 Mode, privilege and stack relationship ........................................................... B1-4

Table B1-2 The xPSR register layout ............................................................................... B1-9

Table B1-3 ICI/IT bit alloca

tion in the EPSR .................................................................. B1-10

Table B1-4 The special-purpose mask registers ............................................................ B1-10

Table B1-5 Exception numbers ...................................................................................... B1-16

Table B1-6 Vector table format ....................................................................................... B1-16

Table B1-7 Priority grouping ........................................................................................... B1-18

Table B1-8 Exception return behavior ............................................................................ B1-26

Table B1-9 List of supported faults ................................................................................. B1-40

Table B1-10 Behavior of faults which occur during NMI or HardFault execution ............. B1-45

Table B3-1 ARMv7-M address map ................................................................................. B3-3

Table B3-2 SCS address space regions ........................................................................... B3-6

Table B3-3 System control and ID registers ..................................................................... B3-7

Table B3-4 Auxiliary Control Register - (0xE000E008) .................................................... B3-9

Table B3-5 CPUID Base Register - (CPUID, 0xE000ED00) .......................................... B3-10

Table B3-6 Interrupt Control and State Register - (0xE000ED04) ................................. B3-12

Table B3-7 Vector Table Offset Register - (0xE000ED08) ............................................ B3-13

List of Tables

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Table B3-8 Application Interrupt and Reset Control Register - (0xE000ED0C) ............. B3-14

Table B3-9 System Control Register (0xE000ED10) ...................................................... B3-15

Table B3-10 Configuration and Control Register (0xE000ED14) ..................................... B3-16

Table B3-11 System Handler Priority Register 1 - (0xE000ED18) ................................... B3-17

Table B3-12 System Handler Priority Register 2 - (0xE000ED1C) .................................. B3-17

Table B3-13 System Handler Priority Register 3 - (0xE000ED20) ................................... B3-17

Table B3-14 System Handler Contro

l and State Register - (0xE000ED24) ..................... B3-18 Table B3-15 Configurable Fault Status Registers (CFSR, 0xE000ED28) ........................ B3-19 Table B3-16 MemManage Status Register (MMFSR, 0xE000D28) ................................. B3-19

Table B3-17 BusFault Status Register (BFSR, 0xE000ED29) ......................................... B3-20

Table B3-18 UsageFault Status Register (UFSR, 0xE000ED2A) ..................................... B3-20

Table B3-19 HardFault Status Register (0xE000ED2C) ................................................... B3-21

Table B3-20 MemManage Address Register (0xE000ED34) ........................................... B3-22

Table B3-21 BusFault Address Register (0xE000ED38) .................................................. B3-22

Table B3-22 Coprocessor Access Control Register- (0xE000ED88) ............................... B3-22

Table B3-23 Software Trigger Interrupt Register - (0xE000EF00) ................................... B3-23

Table B3-24 SysTick register support in the SCS ............................................................ B3-25

Table B3-25 SysTick Control and Status Register - (0xE000E010) ................................ B3-26

Table B3-26 SysTick Reload Value Register - (0xE000E014) ......................................... B3-26

Table B3-27 SysTick Current Value Register - (0xE000E018) ........................................ B3-27

Table B3-28 SysTick Calibration Value Register - (0xE000E01C) .................................. B3-27

Table B3-29 NVIC register support in the SCS ................................................................ B3-30

Table B3-30 Interrupt Controller Type Register - (0xE000E004) ..................................... B3-32

Table B3-31 Interrupt Set-Enable Registers - (0xE000E100-E17C) ................................ B3-33

Table B3-32 Interrupt Clear-Enable Registers - (0

xE000E180-E1FC) ............................ B3-33 Table B3-33 Interrupt Set-Pending Registers - (0xE000E200-E27C) .............................. B3-33

Table B3-35 Interrupt Active Bit Registers - (0xE000E300-E37C) .................................. B3-34

Table B3-36 Interrupt Priority Registers - (0xE000E400-E7F8) ....................................... B3-34

Table B3-34 Interrupt Clear-Pending Registers - (0xE000E280-E2FC) .......................... B3-34

Table B3-37 MPU register support in the SCS ................................................................. B3-39

Table B3-38 MPU Type Register - (0xE000ED90) .......................................................... B3-39

Table B3-39 MPU Control Register - (0xE000ED94) ....................................................... B3-40

Table B3-40 MPU Region Number Register - (0xE000ED98) ......................................... B3-41

Tab le B3-41MPU Regquotesdbs_dbs14.pdfusesText_20

[PDF] [PDF] ARMv7-M Architecture Reference Manual

ARM DDI 0403C_errata_v3 (ID021910)

Reference Manual

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ARMv7-M Architecture Reference Manual

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Architecture Reference Manual.

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Copyright

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Change history

Date Issue Confidentiality Change

June 2006 ANon-confidentialInitial release

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Contents

ARMv7-M Architecture Reference Manual

Preface

Part A Application Level Architecture

Chapter A1 Introduction

Chapter A2 Application Level Programmers' Model

Chapter A3 ARM Architecture Memory Model

Contents

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Chapter A4 The ARMv7-M Instruction Set

Chapter A5 Thumb Instruction Set Encoding

Chapter A6 Thumb Instruction Details

Part B System Level Architecture

Chapter B1 System Level Programmers' Model

Chapter B2 System Memory Model

Contents

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Chapter B3 System Address Map

Chapter B4 ARMv7-M System Instructions

Part C Debug Architecture

Chapter C1 ARMv7-M Debug

Appendix A CPUID

Appendix B ARMv7-M infrastructure IDs

Appendix C Legacy Instruction Mnemonics

Contents

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Appendix D Deprecated Features in ARMv7-M

Appendix E Debug ITM and DWT packet protocol

Appendix F ARMv7-R differences

Appendix G Pseudocode definition

Appendix H Pseudocode Index

Appendix I Register Index

I.3 Memory mapped debug registers ...........

Glossary

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List of Tables

ARMv7-M Architecture Reference Manual

List of Tables

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Table B1-3 ICI/IT bit alloca

List of Tables

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Table B3-14 System Handler Contro

Table B3-32 Interrupt Clear-Enable Registers - (0