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4 nov 2011 · Thumb are registered trademarks and Cortex is a trademark of ARM Limited Other names and brands may be claimed as the property of others 

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Get Better Code Density than 8/16 bit

MCU's

NXP LPC1100 Cortex M0

2

Outline

IntroductionARM Cortex-M0 processor Why processor bit w i dth doesn't ma tte r

Code size

Performance

Cost

Conclusions

3

ARM Cortex-M Processors

A R M Cor tex-A Series: App lica t ions p r ocesso r s for featu r e r i ch

OS and use

r app lication s A R M Cor tex-R Series:

Embedd

ed p r ocesso r s fo r r e a l t ime s i gna l p r ocess i ng and contro l app lications A R M Cor tex-M

Series:

D eeply e m bedded proces so rs optimiz ed fo r mic r o c ontro lle r and lo w power app lica tions

Cortex-M family optimised for deeply embedded

M icrocontroller and low-power applications 4

ARM Cortex-M0 Processor

32-bit ARM RISC processor

T humb 16-bit instruction set

Very power and area optimized

D esigned for low cost, low power

Automatic state saving

o n interrupts and exceptions

Low software overhead on

exception entry and exit

Deterministic instruction execution timing

I nstructi ons always t a k e s t h e s a m e time t o ex e c ut e* *Assumes dete r m i nistic m e m o ry system 5

Thumb instruction set

Thumb ARM7 ARM9

Cortex-A9

Cortex-R4

Cortex-M3

Cortex-M0

Thumb instruction set upwards compatibility

32-bit operations, 16-bit instructions

Introduced in ARM7TDMI ('T'

stands for Thumb)

Supported in every ARM processor developed since

Smaller code footprint

Thumb-2

All processor operations can all be handled in 'Thumb' s tate Enables a performance optimised blend of 16/32-bit instructions

Supported in all Cortex processors

6 Instruction set architectureBased on 16-bit Thumb ISA from ARM7TDMI J ust 56 instructions, all with guaranteed execution time 8 , 16 or 32-bit data transfers possible in one instruction

Thumb-2Sy

ste m , OS

ThumbUser assembl

y co de, compiler generated ADC ADD ADR AND BIC BL BX EOR LDM LDR LDRB LDRSH LSL LSR MOV ORR POP PUSH ROR STM STR STRB STRH TST BKPT BLX CPS REVSH SXTB SXTH UXTB ASR CMN LDRH

MULRSBSUBREV

UXTH NOP WFI SEV WFE YI ELD DMB DSB ISB

MRSMSR

B CMP LDRSB

MVNSBCSVC

REV16 7

Program registers

r0r1r2r3r4r5r6r7r8r9 r10r11r12 r15 (PC)r14 (LR)

All registers are 32-bit wide

I nstructions exist to support 8/16/32-bit dataquotesdbs_dbs21.pdfusesText_27