PERIPHERAL INTERFACING WITH 8086 MICROPROCESSOR: 8255 PPI Overview of 8051 microcontroller, Architecture, I/O ports and Memory organization,
While interfacing memory to 8086 ensure that atleast 4K of ROM is available in It is preferred that clock input to 8253/8254 is derived from the microprocessors
Microprocessors and Microcontrollers/Interfacing with 8086 Lecture Notes Module 3 Learning unit 8: Interface • We have four common types of memory:
When minimum mode operation is select€d, the 8088 or 8086 itself plovides a[ rhe con, aol signals ne€ded to implement the memory and I/O interfaces Fignres 8-
Intel 8086 Microprocessor Architecture, Features, and Signals 63 4 Addressing Modes, Instruction Set, and Programming of 8086 80 5 8086 Interrupts 175 6 Memory and I/O Interfacing 210 7 Features For manual assembling, these
In minimum mode, the 8088 itself provides all the control signals needed to implement the memory and I/O interfaces (see Fig (2)) Fig (2) Block diagram of
microprocessor 8086 3 The remaining address lines of the microprocessor, BHE and A0 are used for decoding the required chip select signals for the odd and
The Input / output organization of computer depends upon the size of Peripherals connected to a computer need special communication links for interfacing them The I/O bus from the processor is attached to all peripherals interface 8086 microprocessor has a much powerful instruction set along with the architectural
Registers are the small additional memory location which are used to store and transfer Swati R Sharma, CE Department 2150707 – Microprocessor and Interfacing 1 Draw the format of a Flag register of an 8086 microprocessor
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Memory Interfacing
1. While interfacing memory to 8086 ensure that atleast 4K of ROM is available in the
beginning locations - starting at 00000H - as IVT is stored in this location.
2. While interfacing memory to 8086 ensure that atleast 4K of ROM is available in the last
locations - ending at location FFFFFH. This is due to the fact that on reset the first instruction is executed from location FFFF0H.
3. The 2K restriction is because the smallest memory chip available is 2K. 2K E and 2K O
adds up to 4K.
4. If you are designing an Embedded System it is okay to use incremental addressing but
while designing a general purpose system it is better to use absolute addressing.
I/O Interfacing
1. All I/O peripherals that are covered in this course are 8-bit so they have to be interfaced
only to D0-D7 or D8-D15 - not to both the buses.
2. If I/O device is connected to D0-D7 then only even addresses must be assigned.
3. If I/O device is connected to D8-D15 then only odd addresses must be assigned.
4. When using fixed addressing - then it is suffice to use Address lines A0-A7 for decoding
and addressing.
5. When using variable addressing - then you need to use Address lines A0-A15 for
decoding and addressing.
6. With I/O mapped I/O IOR and IOW should be used for read and write.
7. If memory mapped I/O use MEMR and MEMW.
8. In case of memory mapped I/O you need to ensure that there is no clash between memory
and I/O address - for eg. address 01000H should not be assigned to both memory and I/O devices.
8255 Interfacing
1. The ports of 8255 in an un-programmed state are input ports- this because if they are
output in unconfigured state and any input device is connected to it - the input device will also be generating an output on the port lines and 8255 will also be producing an output. When two outputs are tied together it results in the destruction one of /both the devices.
2. The output pins of 8255 cannot be used for powering-up devices - as they will not be able
to supply the required driving current.
3. When connecting motors/lamps/speakers etc.. to 8255 - check the current rating of 8255
and the devices - in the case where 8255 is not able to supply the required driving current make use of amplifiers such as 7406 (inverting) and 7407(non-inverting amplifiers. In the case of large current requirements make use of transistors in a Darlington Pair configuration. Click on link below for a brief description of Darlington pair transistors. Darlington Pair.
4. When interfacing Dc motors to 8255 - select appropriate H-Bridges according to motor
specification.
5. H-bridges allows DC motors to run in both directions - you can look at this blog post to
understand how H-Bridges work. H-Bridge operation
6. Port A and Port B can be used only as 8-bit ports - so all pins of Port A/PortB have to be
input or output.
7. Port C can be used as 8-bit port, 4-bit port or as individual port bits in BSR.
8. When connecting AC powered devices to 8255 make use of a relay.
9. When Port A/Port B are programmed in Mode 1/Mode 2 Port C cannot function as
normal I/O port.
8253/8254 Interfacing
1. 8253 works at a maximum clock frequency of 2.6 MHz
2. 8253 does not support read back.
3. It is preferred that clock input to 8253/8254 is derived from the microprocessors clock.
4. As in case of 8255 the 8253 inputs cannot be directly connected to high power devices.
5. Do not connect output from 8253/8254 to 8255 and poll it to find whether it is high or low-
because that defeats the purpose of using a timer. It is better to use timing signals as Interrupts.
8259 Interfacing
1. 8259 has only two addressable - so the order in which the command words are written are
important.
2. OCWs are always written after the ICWs.
3. SP/EN in case of single 8259 - must always be connected to Vcc.
4. Unless you are sure about how long an interrupt request will be held high - do not use
level triggering.
5. Edge triggering is preferred.
6. Since 8086 is used Do of ICW1 will always be set and ICW4 will always have to be
provided.
7. It is preferred that AEOI is not used as this may violate the interrupt priorities.
8. Do not use reserved vector numbers - it is always safe to start with vector 40H.
9. If you have not used AEOI - make sure that a non-specific EOI is given at the end of the
ISR before IRET statement.
10. Make sure that IVT is initialized before using interrupts.
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[PDF] LECTURE NOTES MICROPROCESSORS AND INTERFACING