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ANALYSIS OF CASCADED MULTILEVEL INVERTER

INDUCTION MOTOR DRIVES

Yashobanta Panda

Department of Electrical Engineering

National Institute of Technology, Rourkela

ANALYSIS OF CASCADED MULTILEVEL INVERTER

INDUCTION MOTOR DRIVES

A Thesis submitted in partial fulfillment of the requirements for the degree of

Master of Technology (Research)

in

Electrical Engineering

By

Yashobanta Panda

Roll No.: 60602002

Under the supervision of

Prof. (Dr.) Anup Kumar Panda

Department of Electrical Engineering

National Institute of Technology

Rourkela

DEPARTMENT OF ELECTRICAL ENGINEERING

NATIONAL INSTITUTE OF TECHNOLOGY, ROURKELA

ODISHA, INDIA

CERTIFICATE

This is to certify that the thesis titled Induction Motor Drives submitted to the National Institute of Technology, Rourkela by Mr.Yashobanta Panda, Roll No.60602002 for the award of Master of Technology(Research) in Electrical Engineering, is a bonafide record of research work carried out by him under my supervision and guidance. The candidate has fulfilled all the prescribed requirements.

The Thesis which is based on

degree/diploma.

In my opinion, the thesis is of standard required for the award of a Master of Technology

(Research) degree in Electrical Engineering.

Prof. A. K. Panda

Department of Electrical Engineering

National Institute of Technology

Rourkela 769008

Email: akpanda@nitrkl.ac.in

BIO-DATA OF THE CANDIDATE

Name : Yashobanta Panda

Date of Birth : 20th July. 1978

Permanent Address :At-Mathanuagan

P.O. Kahneipal.

Via-Badasuanlo.

Dist.-Dhenkanal.

PIN.-759039.

ODISHA

e-mail yashelengg2000@gmail.com

ACADEMIC QUALIFICATION

M.Tech (Research) in Electrical Engineering, National Institute of Technology,

Rourkela, Odisha.

ACKNOWLEDGEMENTS

I would like to express my sincere appreciation to my supervisor Prof. A. K. Panda, for his guidance, encouragement, and support throughout the course of this thesis work. It was an invaluable learning experience for me to be one of his students. From him I have gained not only extensive knowledge, but also a careful research attitude. I am very much thankful to Prof. B.D.Subudhi, Head, Department of Electrical Engineering, for his constant support. Also, I am indebted to him for providing me all official and laboratory facilities. I am grateful to my Master Scrutiny Members, Prof.S.Meher and Prof. K. B. Mohanty for their valuable suggestions and comments during this research period. I am especially indebted to my colleagues in the power electronics group. First, I would like to specially thank Mr. Y.Suresh, who helped me in implementing my real time experiments. We share our knowledge & experience in the field of power electronics. I would also like to thank the other members of the team, Mr.Swapnajit Patnaik, Mr. Matada Mahesh, Mr. B.K.Debta, for extending their technical and personal support making my stay pleasant and enjoyable. This section would remain incomplete if Mr. Rabindra Nayak and Mr. Chotta Lal Singh, without whom the work would have not progressed. My heartfelt appreciation goes toward my uncle, Mr. Pratap Kumar Tripathy, my brothers, Jayanta and Jivan and my parents, who were always encouraged me to pursue higher education. With much love, I would like to thank my wife, Susmita, who is always there with her kind and encouraging words. Finally I dedicate this thesis to my son Ayush (Omm).

Y.Panda.

i

CONTENTS

Chapter Title Page No.

Abbreviations iv

List of Figures vi

List of Tables x

Abstract xi

1 INTRODUCTION

1.1 Research Background

1.2 Induction Motor Drives Using Multi-Level Inverter

1.3 Why Cascaded H-bridge multilevel inverter?

1.4 Dissertation Outlines

1 2 5 7 11

2 MULTILEVEL INVERTER STRUCTURES

2.1 Diode-Clamped Multilevel Inverter

2.1.1 Operation of DCMLI

2.1.2 Features of Diode clamped MLI

2.1.3 Advantages and Disadvantages of DCMLI

2.1.4 Conclusion

2.2 Flying Capacitor Structure

2.2.1 Operation of FCML

2.2.2 Features of FCMLI

2.2.3 Advantages and Disadvantages of (FCML)

2.3 Cascaded Multilevel Inverter

2.3.1 Operation of CMI

2.3.2 Features of CMLI

2.3.3 Advantages and Disadvantages of CMI

2.4 Conclusion

12 15 17 19 21
22
22
23
25
25
27
28
29
29
30

3 MODULATION TECHNIQUES FOR MULTI LEVEL

INVERTER

3.1 A Definition of Modulation

3.2 PWM Techniques

31
32
33
ii

3.2.1 Voltage-source methods

I. Sine-triangle modulation

a. Phase Disposition (PD) b. Phase Opposition Disposition (POD) c. Alternate Phase Opposition Disposition (APOD)

II. Space vector modulation

i. Realization of Space Vector PWM ii. Coordinate transformation: abc to dq iii. Output voltages of three-phase inverter iv. Principle of Space Vector PWM v. Basic switching vectors and Sectors

III. Discrete implementation

IV. Space Vector Control

3.2.2 Current-regulated methods

i. Hysteresis control ii. Clocked sigma-delta modulation

3.2.3 Conclusion

3.3 Carrier Based PWM Techniques

3.4 Conclusion

34
36
39
42
45
47
48
49
51
53
53
54
55
56
56
59
59
60
62

4 SIMULATION AND RESULT DISCUSSION

4.1 Simulation of 3-level Cascaded Inverter IM Drive

4.1.1 Simulation Results

4.2 Simulation of 5-level Cascaded Inverter IM Drive

4.2.1 Simulation Results

4.3 Simulation of 5-level Cascaded Inverter IM Drive

4.3.1 Simulation Results

4.4 Comparison

4.5 Experimental setup

4.5.1 Multilevel Inverter(Model No : VPET - 106A)

63
64
65
69
70
74
75
78
79
80
iii

4.5.2 Experimental Results 83

5 CONCLUSION AND FUTURE WORK

5.1 Conclusion

5.2 Future Work

84
85
86

REFERENCES 88

iv

ABBREVIATIONS

FACTS -Flexible AC Transmission Systems

SVG -Static Var Generation

MLI -Multi Level Inverter

CMC -Cascaded Multilevel Converter

CMI -Cascaded Multi-level Inverter

HBBB -H-bridge building block

PWM -Pulse Width Modulation

SVM -Space-Vector Modulation

CM -Common-Mode

NPC -Neutral-Point Clamped

GTO -Gate Turn Off Thyristors

IGBT -Insulated Gate Bipolar Transistor

ARCP -Auxiliary Resonant Commutated Pole

ZVT -Zero-Voltage Transition

SVM -Space Vector Modulation

THD -Total Harmonic Distortion

SHE -Selective Harmonic Elimination

THD -Total Harmonic Distortion

SVC -Space Vector Control

DTC -Direct Torque Control

UPFC -Unified Power-Flow Controller

VSI -Voltage-Source Inverter

v

DCI -Diode Clamped Inverter

FCMLI -Flying Capacitor Multi Level Inverter

IGCT -Integrate Gate Controlled Thyristor

HV -High Voltage

LV -Low Voltage

FPGA -Field Programmable Gate Array

EMC -Electro Magnetic Compatibility

IPM -Intelligent Power Module

SPWM -Sinusoidal Pulse Width Modulation

DC -Direct Current

DSP -Digital Signal Processing

EMI -Electro Magnetic Interference

PLD -Programmable Logic Device

CMI -Common Mode Interference

MPC -Multiple Point Clamped

FPGA SPWM -Field Programmable Gate Arrays -Sinusoidal Pulse Width Modulation vi

LIST OF FIGURES

Fig. No. Title PageNo.

2.1 One Phase Leg of an Inverter With (A) Two Levels, (B) Three Levels,

And (C) N Levels. 14

2.2 Topology of The Diode-Clamped Inverter, (A) Three-Level Inverter,

(B) Five Level Inverter 16

2.3 Output Voltage in Three-Level Diode- Clamped Inverter (A) Leg

Voltage (B) Output Phase Voltage 17

2.4 Capacitor-Clamped Multilevel Inverter Circuit Topologies. (A)

Three-Level Inverter, (B) Five-Level Inverter. 23

2.5 Single Phase Structures of Cascaded Inverter (A) Three-Level,

(B)Five-Level, (C)Seven-Level 27

2.6 Three-Phase 7-Level Cascaded Multilevel Inverter (Y-Configuration) 29

3.1 Pulse-Width Modulation. 33

3.2 Three-Phase Sinusoidal PWM Inverter 37

3.3 Waveforms of Three-Phase Sine PWM Inverter. 37

3.4 Switching Pattern Produced Using The PD Carrier-Based PWM

Scheme: (A) Two Triangles And The Modulation Signal (B) S1ap (C)

S2ap (D) S1an (E) S2an.

41
3.5 Simulation of Carrier-Based PWM Scheme Using the Phase Disposition (PD). (a). Modulation Signal and In-Phase Carrier 42

3.6 Switching Pattern Produced Using The POD Carrier-Based PWM

Scheme: (a) Two Triangles and the Modulation Signal (b) S1ap (c) S2ap (d) S1an (e) S2an. 44

3.7 Simulation of Carrier-Based PWM Scheme Using POD. (a).

vii

Modulation Signal and Phase Carrier Wavefor

Output Voltage.

45

3.8 Simulation of Carrier-Based PWM Scheme Using APOD for a Five-

Level Inverter. (a) Modulation Signal and Carrier Waveforms (b) 46

3.9 Voltage Space Vector And its Components in (d, q) 47

3.10 Three-Phase Power Inverter. 48

3.11 Inverter Voltage Vectors 50

3.12 Basic Switching Vectors and Sectors. 52

3.13 Three-Phase Inverter for Hysteresis Current Control. 53

3.14 57

3.15 Natural PWM in Three Phase Inverter; Phase Leg and Line to Line

Waveforms.

58

3.16 Natural PWM in three phase inverter; phase leg and line to line

waveforms 62

4.1 Three-Level Cascaded Inverter 65

4.2 Carrier-Modulation Signals of 3-Level Cascaded Inverter. 65

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