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Switching Sequence Control Of Reduced Switch

Count Multilevel Inverter With Multi Carrier Pulse

Width Modulation

Kanike Vinod Kumar, R Saravana Kumar

Abstract: Operation of conventional inverters like cascaded Multilevel Inverter (MLI), diode clamped multilevel inverter and flying capacitor multilevel

inverter are easily performed with the various pulse width modulation techniques. The conventional MLIs are not obtaining the good efficiency due to

more switching losses. To attain good efficiency with less switching losses and less Total Harmonic Distortion (THD) without changing the performance

of MLIs, Reduced Switch Multilevel Inverters (RSMLI) are proposed by many researchers. But, the switching operation of RSMLI is not similar to

conventional MLIs which is major task. Operation of individual switch is achieved with the help logic gates. Obtaining the logical equation for each switch

with four proposed RSMLIs are analyzed and presented in this work. To obtain the pulse pattern for each switch, Multi Carrier SPWM (MCSPWM) and

Multi Carrier Unipolar SPWM (MCUPSPWM) methods are used. Binary representation of PWM methods helps the researcher to analyze the switching

sequence and pulse pattern of various RSMLIs with different levels of output voltage. Three 7 level and one 9 level RSMLIs are analyzed and simulated.

%THD comparison is presented for proposed RSMLIs with the various PWM methods by different modulation index values.

Index Terms: Binary pulse representation, Logical Equations, Multi carrier pulse width modulation, Multi carrier unipolar pulse width modulation,

Reduced Switch Multilevel inverter, Switching Sequence, Total Harmonic Distortion.

1. INTRODUCTION

Power conversion is much essential for the operation of many appliances. Converting AC to DC is done with the help of rectifiers and DC to AC conversion is obtained with inverter. From past decades, many researchers are concentrating towards the inverter with reduced switches in design [1], [2], [3], [4], [5], [6], [7], [8], [9]. Many advantages are achieved by various reduced switch inverters as compared with conventional conversion approach. Traditional design operates at instantaneous time and obtains a three level (Quasi Square Wave) inverter. Operating and switching frequency conditions, harmonic content in power conversion, voltage stress on load and switches are some disadvantages of traditional power inverter. To overcome the disadvantages of traditional inverter, Multilevel Inverter (MLI) is used which provides several multi steps as converted output voltage [6]. Several Reduced Switch Multilevel Inverters (RSMLI) are proposed to achieve the cost minimization, optimal voltage stress, reduced power losses, switching frequency operations, less harmonic distortions. support of gating signals (pulses) to the power switches of respective inverter design [1]. Generation of gating signals is achieved by various pulse modulation techniques. Different pulse modulation techniques are proposed by researchers for the operation of MLI. Control and estimation of switching looses and the total harmonic distortion is obtained by modulation techniques [10], [11]. Switching frequency is the important criteria for the operation of MLI. Based on the value of frequency, modulation techniques are categorized into two major types. Fundamental switching frequency with less number of cycles and high switching frequency has repeating signals per cycle. Low switching frequency techniques are selective harmonic elimination, nearest vector control, nearest level control and switching angle control. But, high switching frequency techniques are Space Vector Pulse Width Modulation techniques (SVPWM) and Pulse Width Modulation (PWM) methods [12], [13], [14]. Carrier based modulation technique is highly preferable for the working of various MLI. Pulses generated by comparison of modulating signal and carrier signal are called pulse width modulation technique. Various PWM techniques are presented for the operation of the traditional MLI and reduced switch MLI. Among these modulation methods, multi carrier based PWM is highly preferred and presented for single phase inverter systems [6], [15], [16], [17]. SVPWM, selective harmonic elimination, nearest vector and nearest level control techniques are preferable for the three phase systems [1], [5]. Sequences of switching operation of various RSMLIs are presented in many research works with one of the modulation methods. But, obtaining the required sequence of the pulse pattern is critical part of the presented works. Level shifting and phase shifting multi carrier sinusoidal PWM methods are widely used in the previous works. Unipolar sinusoidal modulating signal is used instead of sinusoidal signal as Unipolar Sinusoidal PWM (USPWM) method. [3], [10], [18]. Obtained pulse pattern from the traditional modulation method is not exactly matching with the required pulse pattern of MLI operation. To achieve the required pulse pattern, basic logic gates are used to convert the generated Kanike Vinod Kumar is currently pursuing PhD in school of electrical engineering in Vellore Institute of Technology, India.

E-mail: kvinuuk.21.vk@gmail.com

R Saravana Kumar is currently working as professor in school of electrical engineering in Vellore Institute of Technology, India. (Corresponding author E-mail: rsaravanakumar@vit.ac.in)

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TABLE 1

REQUIRED COMPONENTS FOR TRADITIONAL MLIS

Type of MLI No. of DC

Sources No. of Switches No. of Capacitors for

DC- bus

Clamping

Capacitors

Clamping

Diodes

Diode Clamped 1 2 x (L-1) L-1 - (L-1) x (L-2)

Flying Capacitor 1 2 x (L-1) L-1 (L-1) x ((L-2)/2) -

Cascaded H-Bridge (L-1)/2 4 x ((L-1)/2) - - -

pulse pattern to required pulse pattern. Analyzing the logic gates for the generation of required pulse pattern is the major task of the MLI operation. Using the logic gates for the researchers work [19], [20], [21], [22], [23], [24], [25], [26], [27], [28]. The operation of MLIs with the required generation of pulse pattern by the application of logic gates is discussed in this paper. Proper explanation is presented with the tabular format for the required pulse pattern to obtain from pulse patterns of multicarrier PWM methods. Section II presents the proposed various multilevel inverters. Various PWM methods with their analysis is given in section III. The operation of RSMLI is presented in section IV. Results and comparison of proposed MLIs are discussed in section V. Section VI gives a brief conclusion of the proposed work on MLIs when the operation of logic gates are considered for producing required pulses.

2 REVIEW ON MLI

Multistep output voltage of the traditional inverter is obtained with the proper arrangement of power semiconductor switches. For the operation of switches in traditional design, bipolar modulating signal is used for the modulation techniques with the carrier signals. Power semiconductor operated and controlled with the pulse patterns obtained from the multicarrier PWM methods. No need to use any intermediate circuit to convert the obtained pattern of pulse to the required pulse pattern [6], [11], [14]. usage of power semiconductor switches, numbers of DC sources, linear and non linear elements are more as given in Table 1. where L is the level of MLI. Because of more number of electrical and electronic components, various parameters like power losses, Total Harmonic Distortion (THD), efficiency, etc, are affecting the traditional MLI designs. To overcome these drawbacks from traditional MLIs, RSMLIs are introduced by many researchers. For the proposed analysis work on PWM, some of the recent RSMLIs are considered from the research work and compared with the performance parameters of the systems. Intermediate switching circuitry is required for the operation of considered RSMLIs. In this work, four RSMLIs are considered for the research. In 2013, a 7 level symmetrical MLI with reduced number of switches like 9 switch topology, 7 switch topology, 6 switch topology and 5 switch topology are proposed [29]. For the operation of these entire reduced switch topologies, 7 level output is presented with the switching sequence tables and the intermediate logical switching circuits. 5 switch topology is considered in this paper and design is shown in Fig. 1. In 2014, 9 level RSMLI is presented with 11 switch symmetric voltage source topology and the design of the proposed MLI shown in Fig. 2. [6]. In this topology, two partitions are presented in the design. One is with high frequency switches for the level generation and the other is for low frequency switches for the polarity generation. In 2015, an asymmetric DC link module cascaded MLI is proposed with reduced switches for 7 level output [14]. This asymmetric MLI consist of 8 switches, 4 for DC link module and 4 for H Bridge. Design of this RSMLI is shown in Fig. 3. Recently, symmetrical cascaded switched diode MLI is proposed for the 7 level output. Design of the proposed RSMLI is combination of two stages. One is for the level shifting with

3 switches and other is for polarity operation with 4 switches

as 7 switch topology [22]. Structure of proposed MLI is shown in Fig. 4.

TABLE 2

REQUIRED COMPONENTS FOR PROPOSED RSMLIS

Year

Voltage

Output

Level

Symmetry /

Asymmetry

No. of

DC

Sources

No. of

Switches

2013[29] 7 Symmetry 4 5

2014[6] 9 Symmetry 4 11

2015[14] 7 Asymmetry 2 8

2019[22] 7 Symmetry 3 7

Fig. 1. Reduced Switch MLI with 5 Switches

Fig.2. Reduced Switch MLI with 11 Switches

Fig.3. Reduced Switch MLI with 8 Switches

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Fig.4. Reduced Switch MLI with 7 Switches

To show the difference on the levels, 7 level and 9 level designs are chosen along with the symmetric and asymmetric voltage sources in the presented structures of MLIs. Among all these proposed methods, the analysis of the switching sequence is clearly mentioned. But, the generated pulse pattern is not exact to the operation of the switching sequence. Analysis of linking generated pulse pattern with the switching sequence pattern is not explained in previous works stated above. Focusing on this analysis for the successful operation of proposed MLIs and is compared with the harmonic content parameters. Table 2. shows the information of switches, DC sources and output level of the various MLIs.

3 MULTI CARRIER PULSE WIDTH MODULATION

METHODS

Operation of power electronic switch and the power flow control in circuit are done with switch-on and switch-off of the switches. This switching process is called modulation. ON and OFF condition of power electronic switch with the help of pulse is called pulse modulation. Parameters of pulse are amplitude and width. If a switch is controlled with the pulse width, then it is PWM. Major types of PWM methods are reference based PWM and carrier based PWM.[6], [7], [11], [17], [30]. In the proposed work, both reference and carrier signals are considered for the analysis of switching sequence. Basically, a sinusoidal (bipolar) signal is considered as reference signal and carrier signal as triangular signal [12], [17], [31]. In most of conventional PWM methods, L-1 carrier signals are used for the L level output voltage. (L-1)/2 carrier signals on positive sinusoidal and remaining on negative side [10]. To reduce the count of carrier signals, Unipolar SPWM method is introduced with half of the carrier signals compared to conventional Multi Carrier SPWM (MCSPWM). Bipolar reference signal is converted to unipolar reference signal without effecting the level of output voltage [6], [7], [11], [32]. Operations of the proposed RSMLIs are analyzed with the application of Multi Carrier Unipolar SPWM (MCUPSPWM) method. This method is applicable for symmetric and asymmetric MLIs without effecting the operation of design. MCSPWM is shown in Fig. 5. Triangular carrier signal arrangement along with unipolar sinusoidal as reference signal is shown in Fig. 6 and 7.

Fig.5. Multi Carrier SPWM for 7 level MLI.

Fig.6. Multi Carrier Unipolar SPWM for 7 level MLI. FIG.7. MULTI CARRIER UNIPOLAR SPWM FOR 9 LEVEL MLI.

TABLE 3

BINARY REPRESENTATION OF PULSE PATTERN FOR 3 TRIANGULAR

CARRIER SIGNALS IN MCUPSPWM METHOD

Time Interval(Sec) Level P3 P2 P1 P0

0 - 0.00125 0V 0 0 0 1

0.00125 - 0.0025 +V 0 0 1 1

0.0025 - 0.00375 +2V 0 1 1 1

0.00375 - 0.005 +3V 1 1 1 1

0.005 - 0.00625 +3V 1 1 1 1

0.00625 - 0.0075 +2V 0 1 1 1

0.0075 - 0.00875 +V 0 0 1 1

0.00875 - 0.01 0V 0 0 0 0

0.01 - 0.01125 0V 0 0 0 0

0.01125 - 0.0125 -V 0 0 1 1

0.0125 - 0.01375 -2V 0 1 1 1

0.01375 - 0.015 -3V 1 1 1 1

0.015 - 0.01625 -3V 1 1 1 1

0.01625 - 0.0175 -2V 0 1 1 1

0.0175 - 0.01875 -V 0 0 1 1

0.01875 - 0.02 0V 0 0 0 1

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TABLE 4

BINARY REPRESENTATION OF PULSE PATTERN FOR 4 TRIANGULAR

CARRIER SIGNALS IN MCUPSPWM METHOD

Time Interval(Sec) Level P4 P3 P2 P1 P0

0 0.001 0V 0 0 0 0 1

0.001 0.002 +V 0 0 0 1 1

0.002 0.003 +2V 0 0 1 1 1

0.003 0.004 +3V 0 1 1 1 1

0.004 0.005 +4V 1 1 1 1 1

0.005 0.006 +4V 1 1 1 1 1

0.006 0.007 +3V 0 1 1 1 1

0.007 0.008 +2V 0 0 1 1 1

0.008 0.009 +V 0 0 0 1 1

0.009 0.01 0V 0 0 0 0 0

0.01 0.011 0V 0 0 0 0 0

0.011 0.012 -V 0 0 0 1 1

0.012 0.013 -2V 0 0 1 1 1

0.013 0.014 -3V 0 1 1 1 1

0.014 0.015 -4V 1 1 1 1 1

0.015 0.016 -4V 1 1 1 1 1

0.016 0.017 -3V 0 1 1 1 1

0.017 0.018 -2V 0 0 1 1 1

0.018 0.019 -V 0 0 0 1 1

0.019 0.02 0V 0 0 0 0 1

To present the clear analysis of switching sequence operation for individual MLI, a binary representation switching sequence is presented in this research work. Binary representation of MCUPSPWM method is shown in Table 3, 4 and 5. Switching sequence of the proposed MLIs are given in Table 6, 7, 8 and

9. Switching sequence of individual MLI with the binary

representation sequence of PWM method to generate the required sequence pulse pattern are compared. As representation of switchi circuit. Analysis of switching sequence is properly explained in the next section.

4 SWITCHING SEQUENCE ANALYSIS AND

SIMULATION WORK

As explained in previous section, L-1 numbers of carrier signals are needed for L level output voltage. For 7 level output voltage, 6 triangular carrier signals are needed and for

9 level, 8 carrier signals are considered. A sinusoidal signal is

considered as modulating signal for MCSPWM. A unipolar sinusoidal signal is used as modulating signal in

MCUPSPWM. Representation of MCSPWM and MCUPSPWM

are shown in Fig 4, 5 and 6. FOR THE OPERATION OF 5 SWITCH TOPOLOGY AND 8 SWITCH TOPOLOGY OF SYMMETRY AND ASYMMETRY S, MCSPWM METHOD IS APPLIED IN THIS WORK. MCUPSPWM IS USED FOR THE OPERATION OF 7 SWITCH

TOPOLOGY AND 11 SWITCH TOPOLOGY WITH

TABLE 5

BINARY REPRESENTATION OF PULSE PATTERN FOR 6 TRIANGULAR CARRIER SIGNALS IN MCSPWM METHOD

Time Interval(Sec) Level P3 P2 P1 PN0 N1 N2 N3

0 - 0.00125 0V 0 0 0 1 1 1 1

0.00125 - 0.0025 +V 0 0 1 1 1 1 1

0.0025 - 0.00375 +2V 0 1 1 1 1 1 1

0.00375 - 0.005 +3V 1 1 1 1 1 1 1

0.005 - 0.00625 +3V 1 1 1 1 1 1 1

0.00625 - 0.0075 +2V 0 1 1 1 1 1 1

0.0075 - 0.00875 +V 0 0 1 1 1 1 1

0.00875 - 0.01 0V 0 0 0 1 1 1 1

0.02 - 0.01125 0V 0 0 0 0 1 1 1

0.01125 - 0.0125 -V 0 0 0 0 0 1 1

0.0125 - 0.01375 -2V 0 0 0 0 0 0 1

0.01375 - 0.015 -3V 0 0 0 0 0 0 0

0.015 - 0.01625 -3V 0 0 0 0 0 0 0

0.01625 - 0.0175 -2V 0 0 0 0 0 0 1

0.0175 - 0.01875 -V 0 0 0 0 0 1 1

0.01875 - 0.02 0V 0 0 0 0 1 1 1

Different output voltage level by symmetry condition of voltage source. Each MLI operation is achieved with the switch sequence pattern presented in Table 6, 7, 8 and 9. Similarly, the pulse pattern of the MCSPWM and MCUPSPWM methods are presented in binary representation for 7 level and 9 level topology in Table 3, 4 and 5. Direct control of each switch is not possible from the generated pulse pattern of PWM methods. Using the binary representation of generated pulse pattern from MCSPWM and MCUPSPWM, switches of proposed MLIs are operated. Each switching sequence pattern of MLI is compared with the pulse pattern of PWM method by binary representation to operate the switch with required switching sequence condition.

Frequency of the proposed system (f) = 50 Hz (1)

Total time period of one cycle (t) = 1/ f = 0.02 sec (2) For 7 level output voltage MLI, total time of one cycle is to be distributed for one cycle of 7 level output voltage as shown in Fig. 8. Similarly, time distribution for 9 level output voltage is shown in Fig. 9. for the analysis of switching pulse pattern generation.

Number of divisions/cycle (Dt) = (L*2) +2 (3)

Time interval of each Dt (td) = [(L*2) +2] / t (4) If a switching sequence is exactly matching with the pulse pattern sequence, then it is using for the operation of proper switch. If switching sequence is not matching with pulse condition of a switch in one cycle, the use of logic gates are decided. If a switch is ON and OFF for more times per cycle, then more number of logic gates are used for the intermediate circuit. With the observation of irregular ON and OFF condition of a switch, some logical equations are analyzed and presented for individual switch which are not having direct control from pulse pattern.

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TABLE 6

SWITCHING SEQUENCE OF 5 SWITCH TOPOLOGY FOR 7 LEVEL MLI.

Level S1 S2 S3 S4 S5

0V 0 0 0 0 0

+V 0 0 1 0 1 +2V 0 1 0 0 1 +3V 1 0 0 0 1 +3V 1 0 0 0 1 +2V 0 1 0 0 1 +V 0 0 1 0 1

0V 0 0 0 0 0

0V 0 0 0 0 0

-V 1 0 0 1 0 -2V 0 1 0 1 0 -3V 0 0 1 1 0 -3V 0 0 1 1 0 -2V 0 1 0 1 0 -V 1 0 0 1 0

0V 0 0 0 0 0

Analysis of switching pulse pattern with the help of binary symmetry and asymmetry MLIs with MCSPWM method. vo WRSRORJ\quotesdbs_dbs11.pdfusesText_17