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Intel 8086 Pin
Functions
280x86 Processor OverviewProduct80088080808580868088802868038680486Pent.Pent.
Pro Year Introduced1972197419761978197919821985198919921995
Clock Rate0.5
-0.82-33-85-105-810-16?16-406660-66+150
Number of Pins1840404040132168273387
Number of transistors30004500650029K29K130K275K1.2M3M5.5M
Number of
instructions66111113133133
Physical Memory16K64K64K1M1M16M16M4GB4GB4GB64G
Virtual Memorynonenonenonenonenone1G64T64T64T64T
Internal Data Bus88816161632326432
External Data Bus8881681616,32326464
Address Bus8161620202424,32323236
Data Types8888,168,168,168,16,328,16,328,16,328,16,32
3MIN MODE SYSTEM
48088/8086 Microprocessor
"Both 40 pin packages "Data bus "Both 16 bit internally "8088 is 8 bit externally ±use AD0-AD7 "8086 is 16 bit externally ±use AD0-AD15 "ALE (Address Latch Enable) Low indicates the data is actually data, not an address "Data but and address bus multiplexed to same pins!
58088/8086 Microprocessor
"Address bus "ALEmust be set high "Most common latch: 74LS373 "Receives AD0-AD7 (8088) or AD0-AD15 (8086) and ALE
68088/8086 Pin Out (Min Mode)
7Pin Out Descriptions
"BHE"Bus High Enable "Distinguishes between upper and lower bytes of a word "Only on 8086
8Pin Out Descriptions
"NMI "Non Maskable Interrupt "Input signal "Causes a jump to the vector table after execution of the current instruction ends
9Pin Out Descriptions
"INTR "Interrupt Request "Processor responds with an interrupt acknowledgement after last cycle of current instruction "Connected to 8259interrupt controller "INTA provided by 8288
10Pin Out Descriptions
"CLK "Clock "Input connected to
8284 clock generator
11Pin Out Descriptions
"RESET "Terminates present activities and discards everything "After reset "CS=FFFFH "DS=0000H "SS=0000H "ES=0000H "IP=0000H "Flags cleared "Queue empty
12Pin Out Descriptions
"READY "Inserts a wait state to handle slower memories when READY
13Pin Out Descriptions
"TEST "Input from the 8087 "Used to synchronize the
8088 and the 8087
"Checked while WAIT instruction executing
14STATUS SIGNALS
"S4,S3 INDICATE
SELECTED SEGMENT
"00 SUPLEMENTRY DATA "01 STACK "10 CODE SEGMENT "11 DATA SEGMENT"S5IS COPY OF
INTERRUPT ENABLE
FLAG "S68086 IS BUS
MASTER (ZERO)
"S7NOT USED IN 8086
15Minimum/Maximum Mode
"Affects functions of pins 24-31 "Minimum Mode "Pins 24-31 are memory and I/O control signals "Control signals generated internally "Similar to 8085A pins "Maximum Mode "Some control signals generated externally "Some pins used for new features "Must be used when using an 8087
16Intel 8086 Max Mode
17MIN & MAX MODE SIGNALS
"Min mode Signals "M/ IO (28) "WR (29) "INTA (24) "DT/R (27) "DEN (26 "ALE (25) "HOLD (30) "HLDA (31)"MAX MODE "QS1 (24) "QS0 (25) "SO (26) "S1 (27) "S2 (28) "LOCK (29) "RQ/GT1 (30) "RQ/GT0 (31)
18Pin Out Descriptions
"MN/MX "Minimum mode = +5V "Maximum mode = Gnd
19Pin Out Descriptions ±Max"QS0, QS1
"Queue status "Status of opcode queue in the processor "00±No operation "01±first byte of an instruction has been taken from queue "10±queue reinitialized (empty "11±subsequent byte from queue has been taken
20Pin Out Descriptions ±Max"S0, S1, S2
"Status Signal Pins (S2-S0) "000 ±INTA ±interrupt acknowledge "001 ±IORC ±read I/O port "010 ±IOWC ±write I/O port "011 ±none - halt "100 ±MRDC ±Instruction fetch "101 ±MRDC ±memory read "110 ±MWTC ±memory write "111 ±none - passive
21Pin Out Descriptions ±Max"LOCK
"Locks processor to system bus "Gain the lock by using LOCKprefix on an assemblyinstruction "Used with status signals to prevent DMA from gaining control of the buses
22Pin Out Descriptions ±Max"RQ/GT0, RQ/GT1
"Request/Grant "Bi-directional "Gain control of local bus "RQ/GT0 normally permanently high (disabled) "RQ/GT1 is connected to the 8087
23Pin Out Descriptions ±Min"INTA
"Interrupt acknowledge "Tells interrupt controller that and INTR has occurred and the vector number is on D0-D7
24Pin Out Descriptions ±Min"ALE
"Address Latch Enable "Indicates a valid address on external data bus
25Pin Out Descriptions
"AD0-AD15 "Shared address/data lines "Content determined byALE
26Using the 74LS373 Address Latch
27Pin Out Descriptions ±Min"DEN
"Data Enable "Enables the 74LS245 "Allows isolation of CPU from system bus
28Pin Out Descriptions ±Min"DT/R
"Controls direction of data flow through
74LS245 Transceiver
29Pin Out Descriptions ±Min"IO/M (8088) or IO/M
(8086) "Address buss accessingmemory or I/O device "8088 ±low when memory "compatible with 8085 "8086 ±high when memory
30Pin Out Descriptions ±Min"WR
"Data on data bus for memory or I/O "Used with Pin 28 forwrites
31Pin Out Descriptions ±Min"HLDA
"Hold Acknowledge "Input on HOLD causes
CPU to respond with
HLDA "Signals DMA controller is allowed to use buses
32Pin Out Descriptions ±Min"HOLD
"From DMA Controller "Requests use of local buses form CPU
33Pin Out Descriptions ±Min"SSO
"8088 only "Used with IO/M and
DT/R to decode status
of current bus cycle
34Minimum Mode Bus Design
"Some control signals need logic gates "Provided by maximum mode "3 Signals provided "RD, WR and IO/M "Generate othersRDWRIO/MSignal
010MEMR
100MEMW
011IOR
101IOW
00XNever happens
35Control Signal Generation (Min Mode)
36Control Signal Generation (Min Mode)
378088 Bus Control ±Min Mode
38Next Time:
"Read the rest of the chapter: "The 8284 Clock Generator & Driver "The 8288 Buss Controller "XT Busesquotesdbs_dbs19.pdfusesText_25
[PDF] Pin Diagram Of 8086 Microprocessor