The HammerBlade: An ML-Optimized Supercomputer for ML and Graphs

A CGRA is a class of reconfigurable architecture that provides word-level granularity in a reconfigurable array to overcome some of the disadvantages of FPGAs For an overview of CGRA architectures, refer to RaPiD [5], ADRES[6] and Mosaic [7]

CGRA - A New Paradigm for Reconfigurable Computing

CGRA - A New Paradigm for Reconfigurable Computing M R Thansekhar and N alaji (Eds ): IIET’14 1565 register to be broadcast to processors in the same row or column respectively IV DISCUSSION Many CGRA-based systems have been proposed in various papers and some of the models have been implemented Each design has different

Designing a Coarse-grained Reconﬁgurable Architecture for

ture (CGRA) The goal of a CGRA is to have the power and performance advantages of an ASIC as well as the cost and ﬂexibility of an FPGA To achieve these goals, our CGRA is designed for datapath computation, rather than general purpose computation We are targeting the application domain encompassing DSP and scientiﬁc computing

Pillars: An Integrated CGRA Design Framework

CGRA design framework, to assist in design space exploration and hardware optimization of CGRA Pillars allows an architect to describe a hierarchical CGRA design in a Scala-based lan-guage and produce an in-memory model for both behavior and structure The model generates the RTL code and the structure for reconﬁguration

SPR: An Architecture-Adaptive CGRA Mapping Tool

CGRA mapping algorithms draw from previous work on compilers for FPGAs and VLIW processors, because CGRAs share features with both devices SPR uses Iterative Modulo Scheduling [16] (IMS), Simulated Annealing [8] placement with a cooling schedule inspired by VPR [3], and PathFinder [11] and QuickRoute [10] for pipelined routing

Data-Flow Graph Mapping Optimization for CGRA with Deep

CGRA as an agent in reinforcement learning (RL), which uniﬁes placement, routing and PE insertion by interchange actions of the agent Experimental results show that RLMap performs comparably to state-of-the-art heuristics in mapping quality, adapts to different architecture and converges quickly Index Terms—CGRA, DFG, Mapping

HiMap: Fast and Scalable High-Quality Mapping on CGRA via

The CGRA Fig 1 An abstract block diagram for a 4x4 CGRA compiler statically determines which operation should execute in which PE at which cycle (placement) and the data routes between the PEs according to the data dependencies (routing) CGRAs are widely used to accelerate compute-intensive loop kernels CGRA compilers exploit the inter

HyCUBE: A CGRA with Reconﬁgurable Single-cycle Multi-hop

CGRA [16], but at the cost of sub-optimal performance of individual loops The N2N connection also makes the map-ping of loops quite challenging for the compiler Indeed, state-of-the-art CGRA compilers spend most of the e ort in nding appropriate routes The DRESC [13] compiler for ADRES adopts a time-consuming simulated annealing approach for

Creating an Agile Hardware Design Flow

CGRA’s processing element (PE), the conﬁguration for the layer mapping applications to the CGRA also needs to change Our main contribution is recognizing that the integra-tion problem is fundamentally about managing the compo-sition of the end-to-end ﬂow’s layers so that the cross-layer