[PDF] Modélisation, caractérisation et analyse de systèmes de PLL



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Modélisation, caractérisation et analyse de systèmes de PLL

Un grand merci aussi à léquipe Alpha Hérouville, pour leur gentillesse, leur accueil et surtout pour certaines séances qui mont fait un bien fou Merci à mes professeurs de Physique/Chimie du collège et du lycée : messieurs Tida et Molliex, qui ont su attiser ma curiosité et mont donné goût aux sciences de lingénieur

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Année 2011

UNIVERSITÉ PARIS

Thèse de

Manohiaina RANAIVONIARIVO

MO , CHAN

OINP SY

U GL CH-PA

-BOAP

DIRECTION ET ENCADREMENT:

Odile PICON Professeur, ESYCOM, Université de Paris Est - Marne la Vallée Sidina WANE Dr.-Ing., Principal, NXP Semiconducteurs Caen

RAPPORTEURS:

Raymond QUÉRÉ Professeur, XLIM, Université de Limoges Junwu TAO Professeur, ENSEEIHT-Laplace, INPT, Université de Toulouse EXAMINATEURS: Fadhel GHANNOUCHI Professeur, Director of iRadio Laboratory , University of Calgary Zhuoxiang REN Professeur, Université Paris-VI Pierre et Marie Curie Patrice GAMAND HDR.-Ing, General Manager ICRF, NXP Semiconducteurs Caen 2 3 4 5 RE

comme tout autre thésard connaitre des hauts et des bas, des très haut et des très bas aussi bien

hercher pour trouver

bien voulu rapporter cette thèse et qui ont donné leur avis favorable afin que je puisse souteni

tieusement ainsi que pour sa confiance projet LoPSTer, merci à

Dominique Lesenechal

de ne pas avoir ménagé ses efforts 6 remonté le moral en des temps parfois assez difficiles. années. Merci à mes parents Mamy et Michelle

dans une certaine sérénité. Merci à Loharanontsoa Moreau et toute sa petite famille pour leur

7 AB compatible ) is coupled with dynamic behavioral non ) and at function block level (nonVCO influence of such as PLL )PLL operating at low power for LNB circuits working at

Key Electromagnetic Couplings, Chip

8 9

RÉSÉ

"Pulling» et de "Pushing» dans les systèmes de boucles à verrouillage de phase (PLL),

niveau puce, niveau assemblage, niveau report sur PCB) sont pris en couplages électromagnétiques ccompatibles ) est couplée à des block de fonction (gain KVCO fonction de la fréquence). effets compétitifs résultant de

masse, etc.) , et des distorsions induites par des éléments extérieurs à la puce (exemple de

développés par NXP PLL fonctionnant aux alentours de 1.736GHz) et à la réceptioPLL de faible ADS

Mots clés

10 11

REMERCIEMENTS

ABSTRACT

GENERAL INTRODUCTION

CHAPTER I:

LINEAR AND NON-INEAR TECHNIQUES FOR BEHAVIORAL MODELING OF PLL SYSTEMS

I.0. Introduction

I.1. Overview of State of the Art of Non

I.1.1. General considerations

a. Baseband, Passband Signals and Modulations

Baseband and Passband signals

Mo b. RF Transmitter c. The Power Amplifier d. Phase Locked Loop Fundamentals

I.1.2. Small

a. Small b. Large

I.1.3. Behavioral Modeling Techniques

I.1.4. Power

I.1.5. Hybrid Models and Co

I.1.6. Measurement Techniques

I.2. Simplification of PLL Systems for Design Specification: Predictive Modeling I.2.1. State of the Art Design of Methodology Challenges for PLL Systems I.2.2. PLL Design Specifications: Importance of Spurs, Pulling and Pushing Effects a. Available Techniques for Pulling Modeling and analysis

Table of Contents:

12 Spice

Analytical Method

LC Oscillator Circuit and Injection

Perturbation Projection Vector (PPV)

Injection pulling in Phase

b. Proposed Solutions in the Literature

Positive use of

Pulling effects reduction

I.3. Context and Originality of the Proposed Contribution

I.3.1. Motivation

I.3.2. The Der

a. To Model Sensitive Active Blocks: b. To tackle Co c. To account for EM Couplings :

I.3.3. The Challenges

a. Simulation and Co b. Measurement/Characterization Challenges:

I.4. Applications Description

I.4.1. An Automotive Car Access Transceiver Application around 868MHz: the a. b. The LoPSTer in an Edible Capsule for Continuous Measurement of Core Body

I.4.2. A Microwave Down

a. The T I.5. Synthesis and Concluding Remarks: Necessity of deriving global

Bibliography of Chapter I

CHAPTER II:

EXPERIMENTAL CHARACTERIZATION AND ANALYSIS OF FREQUENCY PULLING EFFECTS IN PLLS:

APPLICATION TO TRANSCEIVER CASES

II.0. Introduction

II.1. Description of

II.1.1. The Chip

II.1.2. The Package Level Carrier Application

II.1.3. The PCB Level Carrier Application

a. The LoPSTer Test Board Used for Characterization b. An External SAW filter Reported on PCB II.1.4. The Monitoring Characterization Protocol and the Conceivable Measurements a. The Monitoring Characterization Protocol b. The Conceivable Measurements

II.2. Characterization of PLL Pulling

II.2.1. Characterization of PLL Pulling in Frequency Domain a. Spectral Purity of the signal transmitted

Table of contents

b. Phase noise induced by pulling effects c. Qualification of the transmit II.2.2. Characterization of PLL Pulling in Time Domain a. Combination of AM and FM modulation II.3. The Main Directions in the Analysis of Pulling Origins

II.3.1. Main Observations at Function Block Level

a. Influence of the PLL function block on the Pulling

Influence of the Charge Pump on the pulling

Influence of the VCO on the pulling

II.3.2. Main Observations at System Level

a. Effects of the SAW Filter on the Pulling b. Effects of the Power Amplifier on the Pulling

The PA Amplitude Level

The PA output spectrum

c. The Power/ Ground Distribution Network d. Frequency pulling/pushing due to noises on the supplies

Supply of the VCO: noise on Vreg_VCO

Supply of the PA : noise on Vreg_PA

II.3.3. Main Observations at Chip

a. The Parasitic Capacitances Effects II.4. EM Analysis of VCO Pulling in Integrated PLL Systems

II.4.1. The Tank Inductance & Inductive Coupling

II.4.2. Inductive Coupling to Injection Pulling

II.4.3. Importance of Capacitive Coupling

II.4.4. Full

a. Numerical Methods for EM Simulations

The FDTD Method Formulation

The b. EM Simplifications & Assumptions

Layout Topology Simplification

Technology Stack Simplification

Setting Excitation Port

c. EM Coupling Reduction: application on an RX path of a transceiver

II.5. Pulling Analysis in Wireless Chip

II.5.1. Inter

II.6. Synthesis & Conclusion

Bibliography of Chapter II

CHAPTER III:

SYSTEM LEVEL BEHAVIORAL MODELING FOR A PREDICTIVE ANALYSIS OF PULLING EFFECTS IN PLLS

III.0. Introduction

III.1. Basis and Assumptions of Behavioral Modeling for PLL Systems

III.1.1. Assumptions & Simplifications

III.1.2. Methodology of description for Predictive Simulation of PLL Pulling a. To Model Active Sensitive Blocks 14 b. To account for EM Couplings c. To tackle Co d. The Predictive Simulation Approach

III.2. Extraction of

III.2.1. Quasi

III.2.2. Full

III.2.3. Derivation of Broadband Equivalent Circuits for Passive Circuits a. The Approach b. Formulation c. Link of Pole d. Application to VCO inductance

III.2.4. Expression of the Coupling coefficients

a. The approach b. Application to Coupled Metallizations

III.3. Analytical and Semi

III.3.1. Classes of spurs

III.3.2. Modeling of Pulling Effects in Terms of Modulation a. AM modulation b. Combination of AM and FM Modulation

III.4. PLL Function Blocs Analysis & Description

III.4.1. The Reference

III.4.2. The Phase Frequency Detector & the Charge Pump a. The Phase Frequency Detector b. The Charge Pump

III.4.3. The

III.4.4. The Voltage Controlled Oscillator (VCO)

III.4.5. The Feedback Loop and Divider

III.5. Predictive Behavioral Modeling Analysis of PLL Pulling III.5.1. Behavioral Modelling of PLL in Phase Domain a. Feed b. Charge Pump PLL Model c. Pha III.5.2. Methodology & Modeling Approaches for Predictive Simulation of PLL Pulling in a. Assumptions & Simplifications b. Experimental Approach c. The Predictive Simulation Approach d. Implementation

In Matlab/Simulink

In Cadence Virtuoso with a Verilog

III.5.3. Analysis and Discussion on the Predictive Simulations Results III.5.4. Correlation Analysis between Simulations Results & Experimental a. Stability Analysis of PLLs under Frequency Pulling b. Physical Interpretation of Observed Pulling Effects

III.6. Importance of Chip

III.7. Conclusion

Bibliography of Chapter III

Table of contents

GENERAL CONCLUSION................................

A. Conclusion

B. Perceived

APPENDIX

A. Class

A.1. Simplified Description & Principles of Class

A.2. Simplified Analytical Waveforms of Class

A.3. Spectrum of Class

B. D

B.1. De

B.2. Calibration and De

a. Calibration

The TRL method

The SOLT and SOLR methods

The LRM and LRRM methods

b. De

The Probe Pads Structures

De De De

C. Verilog,

C.1. Overview, Description, Functionality of

C.2. Implementation of a PLL with a Verilog

a. The Phase b. The Charge c. The Volta d. The Divider by N

D. Matlab

D.1. Overview, Description, Functionality of Matlab D.2. Implementation of a PLL under VCO pulling with

Bibliography of Appendix

MOD, CARACTANALYSE DE SYSTPLL INTEGR,

APPROCHE GLOBALEPUCE-OITIER-IRCUIT IMPRIM

LIST OF PUBLICATIONS & PATENTS:

16

Figure I.1

Figure I.1

Figure I.1

Figure I.1

Figure I.1

Figure I.1

Figure I.1

Figure I.1

Figure I.2ĭnoise

Figure I.2

Figure I.2

Figure I.2

Figure I.2-

Figure I.3

Figure I.4

Figure I.4

Figure I.4

Figure I.4

at 868MHz

Figure I.4

Figure I.4

Figure I.4

Figure I.4

Figure I.4

Figure II.1

Figure II.1

Figure II.1

Figure II.1RF=868MHz

Figure II.1

Figure II.1

PCB

Figure II.1

Figure II.1

List of Figures:

Table of contents

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