TI-82 GUIDEBOOK - Oregon State University
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Contents
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SPRUFK5A-August2010ReadThisFirstAboutThisManualThisdocumentdescribestheTMS320C674x™megamoduleperipherals.NotationalConventionsThisdocumentusesthefollowingconventions.•Hexadecimalnumbersareshownwiththesuffixh.Forexample,thefollowingnumberis40hexadecimal(decimal64):40h.•Registersinthisdocumentareshowninfiguresanddescribedintables.-Eachregisterfigureshowsarectangledividedintofieldsthatrepresentthefieldsoftheregister.Eachfieldislabeledwithitsbitname,itsbeginningandendingbitnumbersabove,anditsread/writepropertiesbelow.Alegendexplainsthenotationusedfortheproperties.-Reservedbitsinaregisterfiguredesignateabitthatisusedforfuturedeviceexpansion.RelatedDocumentationFromTexasInstrumentsThefollowingdocumentsdescribetheC6000devicesandrelatedsupporttools.CopiesofthesedocumentsareavailableontheInternetatwww.ti.com.Tip:Entertheliteraturenumberinthesearchboxprovidedatwww.ti.com.ThecurrentdocumentationthatdescribestheC6000devices,relatedperipherals,andothertechnicalcollateral,isavailableintheC6000DSPproductfolderat:www.ti.com/c6000.SPRUFE8 - TMS320C674xDSPCPUandInstructionSetReferenceGuide.DescribestheCPUarchitecture,pipeline,instructionset,andinterruptsfortheTMS320C674xdigitalsignalprocessors(DSPs).TheC674xDSPisanenhancementoftheC64x+andC67x+DSPswithaddedfunctionalityandanexpandedinstructionset.SPRUGM5 - TMS320C6742DSPSystemReferenceGuide.DescribestheC6742DSPsubsystem,systemmemory,deviceclocking,phase-lockedloopcontroller(PLLC),powerandsleepcontroller(PSC),powermanagement,andsystemconfigurationmodule.SPRUGJ0 - TMS320C6743DSPSystemReferenceGuide.DescribestheSystem-on-Chip(SoC)includingtheC6743DSPsubsystem,systemmemory,deviceclocking,phase-lockedloopcontroller(PLLC),powerandsleepcontroller(PSC),powermanagement,andsystemconfigurationmodule.
SPRUFK4 - TMS320C6745/C6747DSPSystemReferenceGuide.DescribestheSystem-on-Chip(SoC)includingtheC6745/C6747DSPsubsystem,systemmemory,deviceclocking,phase-lockedloopcontroller(PLLC),powerandsleepcontroller(PSC),powermanagement,andsystemconfigurationmodule.SPRUGM6 - TMS320C6746DSPSystemReferenceGuide.DescribestheC6746DSPsubsystem,systemmemory,deviceclocking,phase-lockedloopcontroller(PLLC),powerandsleepcontroller(PSC),powermanagement,andsystemconfigurationmodule.SPRUGJ7 - TMS320C6748DSPSystemReferenceGuide.DescribestheC6748DSPsubsystem,systemmemory,deviceclocking,phase-lockedloopcontroller(PLLC),powerandsleepcontroller(PSC),powermanagement,andsystemconfigurationmodule.15SPRUFK5A-August2010ReadThisFirstCopyright©2010,TexasInstrumentsIncorporated
RelatedDocumentationFromTexasInstrumentswww.ti.comSPRUG84 - OMAP-L137ApplicationsProcessorSystemReferenceGuide.DescribestheSystem-on-Chip(SoC)includingtheARMsubsystem,DSPsubsystem,systemmemory,deviceclocking,phase-lockedloopcontroller(PLLC),powerandsleepcontroller(PSC),powermanagement,ARMinterruptcontroller(AINTC),andsystemconfigurationmodule.SPRUGM7 - OMAP-L138ApplicationsProcessorSystemReferenceGuide.DescribestheSystem-on-Chip(SoC)includingtheARMsubsystem,DSPsubsystem,systemmemory,deviceclocking,phase-lockedloopcontroller(PLLC),powerandsleepcontroller(PSC),powermanagement,ARMinterruptcontroller(AINTC),andsystemconfigurationmodule.TMS320C674x,TMS320C64x+,C64x+,C674xaretrademarksofTexasInstruments.16ReadThisFirstSPRUFK5A-August2010Copyright©2010,TexasInstrumentsIncorporated
Chapter1SPRUFK5A-August2010Overview
Cache control
Memory protect
Bandwidth Mgmt
L1P 256Instruction fetch
Register
file ARegister
file B C674xFixed/floating point CPU
6464Cache control
Memory protect
Bandwidth Mgmt
L1DCache control
Memory protect
Bandwidth Mgmt
L2 CFG MDMA SDMA EMC 256IDMA 256
256256
Power down
Interrupt
Controller
256256
256256
8x32
32K bytes
L1D RAM/
cacheHigh performance switch fabric64646464Configuration
peripherals bus 3232K bytes
L1P RAM/
cache256K bytesL2 RAM1M bytes
L2 ROM
TagSetOffset
001b4K
010b8K
011b16K
100b32K
101b"MaximalCache."Mapsto32K.110b
Reserved
R-0 15320ReservedL1PMODE
31-3Reserved0Reserved
2h8K 3h16K 4h32KReservedPOPER
R-0R-0
1510ReservedOPER
R-0R/W-0
31-17Reserved0Reserved
L1PInvalidateBaseAddressW-x
Reserved
R-0 150L1PInvalidateWordCountR/W-0
31-16Reserved0Reserved
Reserved
R-0 1510ReservedI
R-0R/W-0
31-1Reserved0Reserved
L1PCFGR/WR
L1PCCR/WR/W
L1PINVR/WR/W
L1PIBARWW
L1PIWCR/WR/W
20.0010.4970.1670.499
30.5011.2470.7511.249
40.9971.9971.3291.999
51.4992.7471.9152.749
62.0013.4972.5013.499
72.4974.2473.0794.249
82.9994.9973.6654.999
Reserved
R-01514131211109876543210
31-16Reserved0Reserved
LockBits31:0W-x
LockBits63:32W-x
LockBits95:64W-x
LockBits127:96W-x
Reserved
R-0153210
ReservedKEYRLOCKUNLOCK
R-0W-0W-0W-0
31-3Reserved0Reserved
Reserved
R-0 1510ReservedLK
R-0R-0
31-1Reserved0Reserved
FaultAddressR-x
31-0FaultAddress0-FFFFFFFFhReserved
Reserved
R-0159876543210
FIDLOCALReservedSRSWReservedURUWReserved
R-0R-0R-0R-0R-0R-0R-0R-0R-0
31-16Reserved0Reserved
Reserved
R-0 1510ReservedMPFCLR
R-0W-0
31-1Reserved0Reserved
L1PMPFARRR
L1PMPFSRRR
L1PMPFCRW/
L1PMPLK0W/
L1PMPLK1W/
L1PMPLK2W/
L1PMPLK3W/
L1PMPLKCMDW/
L1PMPLKSTATRR
L1PMPPAxxR/WR
TagSetOffset
Sub-lineBankByte
001b4K
010b8K
011b16K
100b32K
101bReserved.Mapsto32K110b
Reserved
R-0 15320ReservedL1DMODE
31-3Reserved0Reserved
2h8K 3h16K 4h32KReservedPOPER
R-0R-0
1510ReservedOPER
R-0R/W-0
31-17Reserved0Reserved
Reserved
R-0 1510ReservedI
R-0R/W-0
31-1Reserved0Reserved.
Reserved
R-0 1510ReservedC
R-0R/W-0
31-1Reserved0Reserved
Reserved
R-0 1510ReservedC
R-0R/W-0
31-1Reserved0Reserved
L1DInvalidateBaseAddress(L1DIBAR)W-x
Reserved
R-0 150L1DInvalidateWordCount(L1DIWC)R/W-0
31-16Reserved0Reserved
L1DWritebackBaseAddress(L1DWBAR)W-x
Reserved
R-0 15031-16Reserved0Reserved
L1DCFGR/WR
L1DCCR/WR/W
L1DWIBARWW
L1DWIWCR/WR/W
L1DWBARWW
L1DWWCR/WR/W
L1DIBARWW
L1DIWCR/WR/W
L1DWBR/WR/W
L1DWBINVR/WR/W
L1DINVR/WR
UpperAddressBits1554210
UpperAddressBitsBankNumberOffset
0 0 0 0 00 10001 0000 1 1000
0 0100
11001 11 10 0100 0 0
0 001011001 10 01 101
0 1 1010 101 11 11 11 10 0 0 0 0 0 0
00001 11
10111001 10 00 000
0 1 1010 101 10 01 10 01 1 1 1 1 1 1
0 1010 01
001010 0101 10 11 11111 1 1 1 1
1 11110 0000 1 0000 0 0100
1 0100
0 0010 1 0010 0
0110 0
0 1110 0001 1 0001 0 0101
1 0101
0 0011 1 01 01 0 0111
1 0111
0 0000 0 0100
0 00101
1 000 0 0001 0 0101
0 0011 0 0111
0 0000 0 01 00 0 0001 0 0011