Design compiler upf

  • What is power compiler?

    Overview Power Compiler™ automatically minimizes power consumption at the RTL and gate level, and enables concurrent timing, area, power and test optimizations within the Design Compiler\xae synthesis solution..

Power Compiler takes UPF input and automatically inserts power management cells such as isolation, level-shifter, retention register, power gating and always-on 

Does power compiler support UPF?

It also supports a “golden UPF” flow that preserves original power intent across the entire design flow.
Power Compiler is seamlessly integrated with the Synopsys synthesis design flow and shares the same GUI, commands, constraints and libraries as the Design Compiler and IC Compiler® tools.

How do I use RTL & UPF in design compiler?

Running the RTL and UPF for each block through Design Compiler will create a set of files that acts as an input for block-based place and route using IC Compiler, and for top-level synthesis.

How does IC Compiler integrate UPF constraints into top-level UPF?

that checks the UPF constraints of the top level and the block, and then propagates the block-level constraints up to the top-level UPF.
The same issue is addressed in IC Compiler using the link command, which implicitly executes Design Compiler’s command to integrate the block’s UPF constraints into the top-level UPF.

What is design compiler?

Design Compiler is supplied with the top-level RTL and floorplan, the top SDC and UPF files, and the Block Abstract, as the raw material for a synthesis run to produce an interface-optimized top-level netlist in a .ddc file.
Hence:

  • set_top_implementation_options -block_references {Block1 Block2} -optimize_block_interface true .

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