Design compiler report fanout

How do you fix a high fanout?
Register Duplication During Placement
Figure 11 shows a register with high fan-out to a widely spread area of the chip.
By duplicating this register 50 times, you can reduce the distance between the register and the destinations that ultimately result in faster clock performance..
What is high fanout net synthesis?
High Fanout Net Synthesis (HFNS) is the process of buffering the high fanout nets to balance the load.
High Fanout Net is the net which drives more number of loads.
We set limit for maximum number of loads per net using the command set_max_fanout.
The nets which more than these limit are known as High Fanout Nets..
High Fanout Net is the net which drives more number of loads.
We set limit for maximum number of loads per net using the command set_max_fanout.
The nets which more than these limit are known as High Fanout Nets.
Clock nets, reset, scan enable nets are generally considered as High Fanout Nets.
High Fanout Net Synthesis (HFNS) is the process of buffering the high fanout nets to balance the load.
High Fanout Net is the net which drives more number of loads.
We set limit for maximum number of loads per net using the command set_max_fanout.
The nets which more than these limit are known as High Fanout Nets.

Why do timing reports have high fanout nets?

The reported high fanout nets are typically clock networks.
If that is the case, you will see that the timing reports will have a huge increment in those nets, making timing closure much harder.
Since the high-fanout issue is resolved during Clock Tree Synthesis of the Place & Route phase those timing reports are too pessimistic.

Why is design compiler so bad?

Since items 1) and 2) have a higher default priority than the rest, Design Compiler will often spend an undue amount of time fixing DRC violations on a high fanout net, often at the expense of circuit timing.

How do I get a high fanout -net in design compiler?

In Design Compiler you can use the command all_high_fanout -nets to obtain a collection of nets that has a fanout value bigger than high_fanout_net_threshold variable, which you can review using the command report_app_var high_fanout_net_threshold

A specific threshold N can also defined using the command:

What if a synthesis tool has a high fanout?

2) If the high fanout is real and you can tolerate the slow timings as a result, then increase the fanout limit in your synthesis tool

3) If the high fanout is real and you can NOT tolerate the slow timings, then check that the tool is replicating the signal enough times to reduce the fanout and improve timings

Why do I need a fanout of 200 prior to compile?

prior to compile causes Design Compiler to “pretend” that the net has a fanout of 200 during delay and DRC calculations, regardless of its actual fanout

This will reduce any timing or DRC violations calculated for the net, and can greatly speed up synthesis times

(Pin capacitance is given by the high_fanout_net_pin_capacitance variable)

It's a useful warning : and it's a warning not an error : why do you want to eliminate it? 1) Is the high fanout expected? If not, find out why it...3

Design Compiler computes the delays of high-fanout nets with a simpler model to delimit the computation effort. That can reduce the accuracy of tim...0