Design compiler saif

How do I create a Saif file?
SAIF file can be generated from the VCD file or directly from the simulation tool.
VCD file is Value Change Dump file which is defined in IEEE standard 1364-2001, support the logging of signal and direction.
It is generated bt EDA simulation tool..
What does a Saif file contain?
The SAIF file contains information about static probability and toggle rates of the nets.
It does not contain any information about the simulation vectors used to generate the activities.
To compute power, Power Compiler executes a 0-delay simulation using a set of simulation vectors that it generates..
What is the difference between Fsdb and Saif?
Later, a power estimation tool fed with a SAIF file calculates the average power consumption of the whole circuit, or an FSDB file is used to compute the peak power in time and space of the design (see Figure 1)..
Later, a power estimation tool fed with a SAIF file calculates the average power consumption of the whole circuit, or an FSDB file is used to compute the peak power in time and space of the design (see Figure 1).
The SAIF file contains information about static probability and toggle rates of the nets.
It does not contain any information about the simulation vectors used to generate the activities.
To compute power, Power Compiler executes a 0-delay simulation using a set of simulation vectors that it generates.

Sep 18, 2008Hi, When I try to read in the saif file into design compiler, which is created from the vcd file generated from rtl simulation in modelsim, Annotating switching activity | Forum for ElectronicsProblem with annotating switching activity !!! | Forum for Electronicspower analysis using synopsys DC compiler | Forum for ElectronicsRe: Problems with DesignCompiler/PrimeTime FlowMore results from www.edaboard.com

Note that this tutorial is based on the vtvt_tsmc180 library. Using Design Compiler, you first need to generate a forward saif file. Then include the forward

Using Design Compiler, you first need to generate a forward saif file. Then include the forward saif file in your testbench to generate a backward annotated saif file. Finally, read the backward saif file back to perform the power estimation.

Using Design Compiler, you first need to generate a forward saif file. Then include the forward saif file in your testbench to generate a backward annotated

Generate A Backward Saif File

Compile and elaborate your design, and set your simulation environment to call UCLI (Unified Command Line Interface) to run Verilog SAIF commands.

Generate A Forward Saif File

Please downlod these sample two codes into :

How do I use design compiler?

Using Design Compiler, you first need to generate a forward saif file.
Then include:

the forward saif file in your testbench to generate a backward annotated saif file.
Finally, read the backward saif file back to perform the power estimation.
You must set up your Synopsys environment prior to running this tutorial.

How do I use VHDL Saif?

Compile and elaborate your design, and set your simulation environment to call UCLI (Unified Command Line Interface) to run VHDL SAIF commands.
The ucli prompt appears.
You may now generate the backward SAIF file or the VCD file to get power estimation.
If you intend to use Power Compiler, you will need the SAIF for power estimation.

How to generate a Saif file using DC shell XG-T?

Type dc_shell-xg-t in UNIX prompt.
Design Compiler starts.
Type source cnt_updown_fw.scr at the DC Shell prompt.
The Verilog synthesized design cnt_updown_syn_power.v and the saif file cnt_updown_fw.saif of the counter are generated. 2.
Generate a backward saif file .

What information does the Saif file contain?

The SAIF file contains information about static probability and toggle rates of the nets.
It does not contain any information about the simulation vectors used to generate the activities.
To compute power, Power Compiler executes a 0-delay simulation using a set of simulation vectors that it generates.