Design compiler register retiming reference manual

However, the pipeline_design and balance_register commands can be applied to only edge-triggered registers in the current release.
Register retiming is a sequential optimization technique that moves registers through the combinational logic gates of a design to optimize timing and area.

Select Design Compiler, then select a release in the list that appears at the bottom.
The Design Compiler Register Retiming Reference Manual describes the concepts of register retiming and shows you how to use this capability to retime circuits.
Register retiming performs a sequential optimization that moves registers to optimize timing and area.

Register retiming further improves QoR.
It performs optimization of sequential logic by moving registers through logic boundaries to optimize timing with minimum area impact (Figure 6) for designs that already contain registers.
The same functionality is preserved at I/O boundaries.

With register retiming, the locations of the flip-flops in a sequential design can be automatically adjusted to equalize as nearly as possible the delays of the stages.
This capability is particularly useful when some stages of a design exceed the timing goal while other stages fall short.