Design compiler timing

Jul 10, 20201. This is the timing report for a single ALU module synthesis results. The critical path goes through the divider. 2. This is the timing report for a whole 5  difference between design compiler and prime timeStrange timing problem of design compiler - Forum for Electronics[SOLVED] - Design Compiler vs. Prime Time: Setup ViolationsDesign Compiler(DC) Optimization commands to reduce negative More results from www.edaboard.com

Jul 10, 2020The critical path timing result for the whole processor is around 1.5ns, lies on the execution stage. I use "compile effort high" and I can see every component  worst case timing of a sub-module using synopsys design compiler[SOLVED] - Design Compiler vs. Prime Time: Setup ViolationsStrange timing problem of design compiler - Forum for ElectronicsDC : combinational timing loop - Forum for ElectronicsMore results from www.edaboard.com

Concurrent Timing, Area, Power, and Test Optimization. Design Compiler® RTL synthesis solution enables users to meet today's design challenges with concurrent 

• From the menu, choose: Timing → Report Timing Path. • If you wish, you can Design Compiler to search for the existing databases in the Design Compiler