Computer architecture interrupts

In digital computers, an interrupt is a request for the processor to interrupt currently executing code, so that the event can be processed in a timely manner.
If the request is accepted, the processor will suspend its current activities, save its state, and execute a function called an interrupt handler to deal with the event.
This interruption is often temporary, allowing the software to resume normal activities after the interrupt handler finishes, although the interrupt could instead indicate a fatal error.

In computer systems programming, an interrupt handler, also known as an interrupt service routine or ISR, is a special block of code associated with a specific interrupt condition.
Interrupt handlers are initiated by hardware interrupts, software interrupt instructions, or software exceptions, and are used for implementing device drivers or transitions between protected modes of operation, such as system calls.

In computing, interrupt latency refers to the delay between the start of an Interrupt Request (IRQ) and the start of the respective Interrupt Service Routine (ISR).
For many operating systems, devices are serviced as soon as the device's interrupt handler is executed.
Interrupt latency may be affected by microprocessor design, interrupt controllers, interrupt masking, and the operating system's (OS) interrupt handling methods.

In a computer, an interrupt request is a hardware signal sent to the processor that temporarily stops a running program and allows a special program, an interrupt handler, to run instead.
Hardware interrupts are used to handle events such as receiving data from a modem or network card, key presses, or mouse movements.

Message Signaled Interrupts (MSI) are a method of signaling interrupts, using special in-band messages to replace traditional out-of-band signals on dedicated interrupt lines.
While message signaled interrupts are more complex to implement in a device, they have some significant advantages over pin-based out-of-band interrupt signalling, such as improved interrupt handling performance.
This is in contrast to traditional interrupt mechanisms, such as the legacy interrupt request (IRQ) system.

In computing, a non-maskable interrupt (NMI) is a hardware interrupt that standard interrupt-masking techniques in the system cannot ignore.
It typically occurs to signal attention for non-recoverable hardware errors.
Some NMIs may be masked, but only by using proprietary methods specific to the particular NMI.

In computing, a programmable interrupt controller (PIC) is an integrated circuit that helps a microprocessor handle interrupt requests (IRQ) coming from multiple different sources which may occur simultaneously.
It helps prioritize IRQs so that the CPU switches execution to the most appropriate interrupt handler (ISR) after the PIC assesses the IRQ's relative priorities.
Common modes of interrupt priority include hard priorities, rotating priorities, and cascading priorities.
PICs often allow mapping input to outputs in a configurable way.
On the PC architecture PIC are typically embedded into a southbridge chip whose internal architecture is defined by the chipset vendor's standards.

In computer science, a vectored interrupt is a processing technique in which the interrupting device directs the processor to the appropriate interrupt service routine.
This is in contrast to a polled interrupt system, in which a single interrupt service routine must determine the source of the interrupt by checking all potential interrupt sources, a slow and relatively laborious process.