10. Selectable I/O Standards in Cyclone II Devices









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I II III IV V VI VII VIII IX X XI XII XIII USG ASG D-2 D-1 P-5 P-4 P-3 P-2

I. II. III. IV. V. VI. VII. VIII. IX. X. XI. XII. XIII. USG. 301443. ASG. 278


10. Selectable I/O Standards in Cyclone II Devices

Altera recommends an input voltage range of. – 0.5 V ≤VI ≤4.1 V. Differential HSTL-15 class I or class II. Pseudo differential (3). (4).


21448810. Selectable I/O Standards in Cyclone II Devices

Altera Corporation 10-1

February 2008

10. Selectable I/O Standards

in Cyclone II Devices

Introduction

The proliferation of I/O standards and the need for improved I/O performance have made it critical that low-cost devices have flexible I/O capabilities. Selectable I/O capabilities such as SSTL-18, SSTL-2, and

LVDS compatibility allow Cyclone

II devices to connect to other devices

on the same printed circuit board (PCB) that may require different operating and I/O voltages. With these aspects of implementation easily manipulated using the Altera

Quartus

II software, the Cyclone II

device family allows you to use low cost FPGAs while keeping pace with increasing design complexity. This chapter is a guide to understanding the input and output capabilities of the Cyclone II devices, including: ?Supported I/O standards ?Cyclone II I/O banks ?Programmable current drive strength ?I/O termination ?Pad placement and DC guidelines fFor information on hot socketing, refer to the Hot Socketing & Power-On Reset chapter in volume 1 of the Cyclone II Device Handbook. For information on ESD specifications, refer to the Altera Reliability Report.

Supported I/O

Standards

Cyclone II devices support the I/O standards shown in Table 10-1. fFor more details on the I/O standards discussed in this section, including target data rates and voltage values for each I/O standard, refer to the DC Characteristics and Timing Specifications chapter in volume 1 of the Cyclone II Device Handbook.

CII51010-2.4

10-2Altera Corporation

Cyclone II Device Handbook, Volume 1 February 2008Supported I/O Standards fFor information about the I/O standards supported for external memory applications, refer to the External Memory Interfaces chapter in volume 1 of the Cyclone II Device Handbook. Table 10-1. Cyclone II Supported I/O Standards and Constraints (Part 1 of 2)

I/O Standard Type

V CCIO

LevelTop and

Bottom I/O

PinsSide I/O Pins

Input Output

CLK,

DQSUser I/O

PinsCLK,

DQSPLL_OUTUser I/O

Pins

3.3-V LVTTL and LVCMOS Single ended 3.3 V/

2.5 V3.3 V

vvv v v

2.5-V LVTTL and LVCMOS Single ended 3.3 V/

2.5 V2.5 V

vvv v v

1.8-V LVTTL and LVCMOS Single ended 1.8 V/

1.5 V1.8 V

vvv v v

1.5-V LVCMOS Single ended 1.8 V/

1.5 V1.5 V

vvv v v

SSTL-2 class I Voltage

referenced2.5 V 2.5 V vvv v v

SSTL-2 class II Voltage

referenced2.5 V 2.5 V vvv v v

SSTL-18 class I Voltage

referenced1.8 V 1.8 V vvv v v

SSTL-18 class II Voltage

referenced1.8 V 1.8 V vv (1) (1) (1)

HSTL-18 class I Voltage

referenced1.8 V 1.8 V vvv v v

HSTL-18 class II Voltage

referenced1.8 V 1.8 V vv (1) (1) (1)

HSTL-15 class I Voltage

referenced1.5 V 1.5 V vvv v v

Altera Corporation 10-1

February 2008

10. Selectable I/O Standards

in Cyclone II Devices

Introduction

The proliferation of I/O standards and the need for improved I/O performance have made it critical that low-cost devices have flexible I/O capabilities. Selectable I/O capabilities such as SSTL-18, SSTL-2, and

LVDS compatibility allow Cyclone

II devices to connect to other devices

on the same printed circuit board (PCB) that may require different operating and I/O voltages. With these aspects of implementation easily manipulated using the Altera

Quartus

II software, the Cyclone II

device family allows you to use low cost FPGAs while keeping pace with increasing design complexity. This chapter is a guide to understanding the input and output capabilities of the Cyclone II devices, including: ?Supported I/O standards ?Cyclone II I/O banks ?Programmable current drive strength ?I/O termination ?Pad placement and DC guidelines fFor information on hot socketing, refer to the Hot Socketing & Power-On Reset chapter in volume 1 of the Cyclone II Device Handbook. For information on ESD specifications, refer to the Altera Reliability Report.

Supported I/O

Standards

Cyclone II devices support the I/O standards shown in Table 10-1. fFor more details on the I/O standards discussed in this section, including target data rates and voltage values for each I/O standard, refer to the DC Characteristics and Timing Specifications chapter in volume 1 of the Cyclone II Device Handbook.

CII51010-2.4

10-2Altera Corporation

Cyclone II Device Handbook, Volume 1 February 2008Supported I/O Standards fFor information about the I/O standards supported for external memory applications, refer to the External Memory Interfaces chapter in volume 1 of the Cyclone II Device Handbook. Table 10-1. Cyclone II Supported I/O Standards and Constraints (Part 1 of 2)

I/O Standard Type

V CCIO

LevelTop and

Bottom I/O

PinsSide I/O Pins

Input Output

CLK,

DQSUser I/O

PinsCLK,

DQSPLL_OUTUser I/O

Pins

3.3-V LVTTL and LVCMOS Single ended 3.3 V/

2.5 V3.3 V

vvv v v

2.5-V LVTTL and LVCMOS Single ended 3.3 V/

2.5 V2.5 V

vvv v v

1.8-V LVTTL and LVCMOS Single ended 1.8 V/

1.5 V1.8 V

vvv v v

1.5-V LVCMOS Single ended 1.8 V/

1.5 V1.5 V

vvv v v

SSTL-2 class I Voltage

referenced2.5 V 2.5 V vvv v v

SSTL-2 class II Voltage

referenced2.5 V 2.5 V vvv v v

SSTL-18 class I Voltage

referenced1.8 V 1.8 V vvv v v

SSTL-18 class II Voltage

referenced1.8 V 1.8 V vv (1) (1) (1)

HSTL-18 class I Voltage

referenced1.8 V 1.8 V vvv v v

HSTL-18 class II Voltage

referenced1.8 V 1.8 V vv (1) (1) (1)

HSTL-15 class I Voltage

referenced1.5 V 1.5 V vvv v v
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