[PDF] ARM Assembly Language Tools v18.1.0.LTS Users Guide (Rev. U)

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ARMAssemblyLanguageToolsv18.1.0.LTS

www.ti.com www.ti.com www.ti.com www.ti.com www.ti.com www.ti.com www.ti.com www.ti.com www.ti.com {printf("helloworld\n");}

B,bSuffix - binaryintegerH,hSuffix - hexadecimalintegerLSBLeastsignificantbitMSBMostsignificantbit0xPrefix - hexadecimalintegerQ,qSuffix - octalinteger

RelatedDocumentationFromTexasInstrumentswww.ti.com14SPNU118U-January2018SubmitDocumentationFeedbackCopyright©2018,TexasInstrumentsIncorporatedReadThisFirstRelatedDocumentationFromTexasInstrumentsSeethefollowingresourcesforfurtherinformationabouttheTICodeGenerationTools:•TexasInstrumentsWiki:Compilertopics•TexasInstrumentsE2ECommunity:CompilerforumYoucanusethefollowingbookstosupplementthisuser'sguide:SPNU151 - ARMOptimizingC/C++CompilerUser'sGuide.DescribestheARMC/C++compiler.ThisC/C++compileracceptsANSIstandardC/C++sourcecodeandproducesassemblylanguagesourcecodefortheARMplatformofdevices.SPNU134 - TMS470R1xUser'sGuide.DescribestheTMS470R1xRISCmicrocontroller,itsarchitecture(includingregisters),ICEBreakermodule,interfaces(memory,coprocessor,anddebugger),16-bitand32-bitinstructionsets,andelectricalspecifications.Trademarks

C/C++ source files C/C++ compiler

Assembler

source

Assembler

Executable

object file

Debugging

toolsLibrary-build utility

Run-time-

support library

Archiver

Archiver

Macro library

Absolute lister

Hex-conversion

utility

Cross-reference

listerObject file utilitiesARM

Linker

Macro source files

Object

files EPROM programmer

Library of

object files

C/C++ name

demangling utility

Object file

.bss .data .text RAM

EEPROM

ROM

Target memory

.data file1 (.bss) file2 (.bss) file1 (.data) file2 (.data) file1 (.text) file2 (.text)

InitExecutable

object module Init (named section) .datafile1.obj .text .bss

Tables

(named section) .datafile2.obj .text .bss

Memory map

Tables

Init

TablesSpace for

variables (.bss)

Initialized

data (.data)

Executable

code (.text) ldb*a3++,b5subb0,1,b0;decrementcounter copy_done:

C auto init

table and data (ROM) .data uninitialized (RAM) Boot routine .cinit sectionLoader

Object file Memory

.data section (initialized) (RAM) .data sectionLoader

Object file Memory

C/C++ source files C/C++ compiler

Assembler

source

Assembler

Executable

object file

Debugging

toolsLibrary-build utility

Run-time-

support library

Archiver

Archiver

Macro library

Absolute lister

Hex-conversion

utility

Cross-reference

listerObject file utilitiesARM

Linker

Macro source files

Object

files EPROM programmer

Library of

object files

C/C++ name

demangling utility

Windows:c:\tools\files\copy.asm

4.6.3.1OperandSyntaxesforInstructionsTheassemblerallowsyoutospecifythatanoperandshouldbeusedasanaddress,animmediatevalue,anindirectaddress,aregister,ashiftedregister,oraregisterlist.Thefollowingrulesapplytotheoperandsofinstructions.•#prefix - theoperandisanimmediatevalue.Usingthe#signasaprefixcausestheassemblertotreattheoperandasanimmediatevalue.Thisistrueeveniftheoperandisaregister;theassemblertreatstheregisterasavalueinsteadofusingthecontentsoftheregister.Forexample:Label:ADDR1,R1,#123;Add123(decimal)tothevalueofR1andplacetheresultinR1.•Squarebrackets - theoperandisanindirectaddress.Iftheoperandisenclosedinsquarebrackets,theassemblertreatstheoperandasanindirectaddress;thatis,itusesthecontentsoftheoperandasanaddress.Indirectaddressesconsistofabaseandanoffset.Thebaseisspecifiedbyaregisterandisformedbytakingthevalueintheregister.Theoffsetcanbespecifiedbyaregister,animmediatevalue,orashiftedregister.Furthermore,theoffsetcanbedesignatedasoneofthefollowing:

www.ti.comSourceStatementFormat51SPNU118U-January2018SubmitDocumentationFeedbackCopyright©2018,TexasInstrumentsIncorporatedAssemblerDescriptionTheoffsetcanbeaddedtoorsubtractedfromthebase.Thefollowingareexamplesofinstructionsthatuseindirectaddressesasoperands:A:LDRR1,[R1];LoadfromaddressinR1intoR1.LDRR7,[R1,#5];FormaddressbyaddingthevalueinR1to5.LoadfromaddressintoR7.STRR3,[R1,-R2];FormaddressbysubtractingthevalueinR2fromthevalueinR1.StorefromR3;tomemoryataddress.STRR14,[R1,+R3,LSL#2];FormaddressbyaddingthevalueinR3shiftedleftby2tothevalueinR1.;StorefromR14tomemoryataddress.LDRR1,[R1],#5;LoadfromaddressinR1intoR1,thenadd5totheaddress.STRR2,[R1],R5;StorevalueinR2intheaddressinR1,thenaddthevalueinR5totheaddress.•!suffix - write-backtoregister.Ifyouusethe!signasasuffix,theassemblerwritesthecomputedaddressbacktothebaseregister.Write-backtoregisterisusedonlywiththeindirectaddressingmodesyntax.Thisisanexampleofaninstructionusingthewritebacktoregistersuffix:LDRR1,[R4,#4]!;FormaddressbyaddingthevalueinR4to4.LoadfromthisaddressintoR1,;thenreplacethevalueinR4withtheaddress.•^suffix - setSbit.Ifyouusethe^signasasuffix,theassemblersetstheSbit.TheresultingactiondependsonthetypeofinstructionbeingexecutedandwhetherR15isinthetransferlist.Formoreinformation,seetheLDMandSTMinstructionsintheTMS470R1xUser'sGuide.LDMIASP,{R4-R11,R15}^;LoadregistersR4throughR11andR15frommemoryatSP.LoadCPSRwithSPSR.•Shiftedregisters.Ifaregistersymbolisfollowedbyashifttype,thecomputedvalueisthevalueintheregistershiftedaccordingtothetypeasdefinedbelow:LSL

LSR ASL ASR ROR 3.14 3. -0.314e13 +314.59e-2 $$strtod("0x1.234p-5") $$strtod("NaN") $$strtod("Inf") .byteSYM2*SYM2;Unequalvalues.endif .byteSYM1;Greaterthan.endif .byteSYM4+SYM4;Equalvalues.endif

R0A1R8V5

R1A2R9V6

R2A3R10V7

R3A4R11V8

R4V1R12V9,IPR5V2R13SP

R6V3R14LR

R7V4,APR15PC

(1)OperatorDescription (2)1+ %Multiplication

Division

Modulo

3+ -Addition

Subtraction

4<<>>ShiftleftShiftright5<

absoluterelocatablerelocatableillegal absoluteexternalexternalillegal relocatablerelocatableillegalabsolute (1)relocatableexternalillegalillegal externalabsoluteexternalexternal externalrelocatableillegalillegal externalexternalillegalillegal

1 00000000 .state32

2.copy !mac1.inc!

A 1 to16 .macro

A 2ADD r0, pc, #1

A 3BX r0

A 4.state16

A 5

A 6.endm

3

4.global __stack

5 ;***********************************************

6 ;* DEFINE THE USER MODE STACK **

7 ;***********************************************

8 00000200 STACKSIZE .set 512

9 00000000 __stack: .usect !.stack!, STACKSIZE, 4

10 ;***********************************************

11 ;* INTERRUPT VECTORS **

12 ;***********************************************

13.global reset

14 00000000 .sect !.intvecs!

15

16 00000000EAFFFFFE" B reset

17 0000000400000000 .word 0

18 0000000800000000 .word 0

19 0000000c00000000 .word 0

20 0000001000000000 .word 0

21 0000001400000000 .word 0

22 0000001800000000 .word 0

23 0000001c00000000 .word 0

24

25 00000000 .text

26.global dispatch

27.global reset

28 ;***********************************************

29 ;* RESET ROUTINE**

30 ;***********************************************

31 00000000 reset:

32;*####################################

33;* SET TO USER MODE

34;*####################################

35 00000000E10F0000 MRS r0, cpsr

36 00000004E3C0001F BIC r0, r0, #0x1F ; Clear modes

37 00000008E3800010 ORR r0, r0, #0x10 ; Set user mode

38 0000000cE129F000 MSR cpsr, r0

39

Field 1 Field 2 Field 3 Field 4

Include file

letter

Line number

40;*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

41;* CHANGE TO 16 BIT STATE

42;*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

43 00000010 to16

1 00000010E28F0001 ADD r0, pc, #1

1 00000014E12FFF10 BX r0

1 00000018 .state16

1 44

45;*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

46;* INITIALIZE THE USER MODE STACK

47;*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

48 000000184802 LDR r0, stack

49 0000001a4685 MOV sp, r0

50 0000001c4802 LDR r0, stacksz

51 0000001e4485 ADD sp, r0

52

53;*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

54;* DISPATCH TASKS

55;*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

56 00000020F7FF! BL dispatch

00000022FFEE

57 0000002400000000!stack .long __stack

58 0000002800000200 stacksz .long STACKSIZE

59
60
61

Nesting level

number

Field 1 Field 2 Field 3 Field 4

intm1;intm2;}X;Xsvar={1,2};Example4 .text topic 31

0 0 00

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0

313029

0 0 028 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 0

0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0

31

0 1 122 21 20 19 180

0 0 1 0 0 0 1 0 0 0 0

31

0 1 128 27 26 25 24 230

0 0 1 0 0 0

313029

0 1 1 .field 3,3 .field 8,6 .field 16,5 .field 01234h,20 .field 01234h,32

3 bits

6 bits

5 bits

20 bits

02h 04h

Current

SPC = 03h

New SPC = 04h

after assembling .align 2 directive2 bytes (a) Result of .align 2 08h 0Ch

Current

SPC = 0AhNew SPC = 0Ch

after assembling .align directive1 word (b) Result of .align without an argument

17 bytes

reserved

20 bytes

reserved

Res_1 = 08h

Res_2 = 33h

.break .emsg.eval .fclist .fcnolist.length .mlist .mmsg.mnolist .sslist .ssnolist.var .width .wmsg

4.asgR13,STACKPTR5.asg&,AND6

(sourcefile)byte.asm (firstcopyfile)word.asm (sourcefile)byte2.asm (firstcopyfile)word2.asm S E E E E E E E E E E E M M M M M M M M M M M M M M M M M M M M

31 200

M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M 0 31

Legend:S = signE = exponent (11-bit biased)

M = mantissa (52-bit fraction)

.drnolist .asg1,x.loop3.evalx+1,x.endloop

8.drnolist12.loop313.evalx+1,x14.endloop

.word0

ADDparm1,r7,r8.endif

.endm

MSG_EXR0MSG_EX

.ifAAAADDR0,R0,#1024.else

ADDR0,R0,#1024*10.endif

.fcnolist .ifAAAADDR0,R0,#1024.else

ADDR0,R0,#1024*10.endif

Listingfile:***ARM***

11.fcnolist12

1400000004E2800B01ADDR0,R0,#1024

31

0 0 00

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 1

31

1 1 00

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