[PDF] CY7C1371S 18-Mbit (512K × 36) Flow-Through SRAM with NoBL

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CY7C1371S

18-Mbit (512K × 36) Flow-Through SRAM

with NoBL™ Architecture

Cypress Semiconductor Corporation• 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 001-43826 Rev. *F Revised March 18, 2016

18-Mbit (512K × 36) Flow-Through SRAM with NoBL™ ArchitectureFeatures

?No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles ?Supports up to 133-MHz bus operations with zero wait states ?Data is transferred on every clock

?Pin-compatible and functionally equivalent to ZBT™ devices ?Internally self-timed output buffer control to eliminate the need

to use OE ?Registered inputs for flow through operation ?Byte Write capability ?3.3 V/2.5 V I/O power supply (V DDQ ?Fast clock-to-output times ?6.5 ns (for 133-MHz device) ?Clock Enable (CEN) pin to enable clock and suspend operation?Synchronous self-timed writes ?Asynchronous Output Enable ?Available in JEDEC-standard Pb-free 100-pin TQFP, and non

Pb-free 119-ball BGA

?Three chip enables for simple depth expansion ?Automatic Power down feature available using ZZ mode or CEdeselect ?IEEE 1149.1 JTAG-Compatible Boundary Scan ?Burst Capability - linear or interleaved burst order?Low standby power

Functional Description

The CY7C1371S is a 3.3 V, 512K × 36 Synchronous flow through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations with no wait state insertion. The CY7C1371S is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write opera- tions with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device). Write operations are controlled by the two or four Byte Write

Select (BWX

) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE

1 , CE 2 , CE 3 ) and an asynchronous Output Enable (OE ) provide for easy bank selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.Selection Guide

Description133 MHzUnit

Maximum Access Time6.5 ns

Maximum Operating Current210 mA

Maximum CMOS Standby Current70 mA

CY7C1371S

Document Number: 001-43826 Rev. *F Page 2 of 29

Logic Block Diagram - CY7C1371S

CMODE BWA BWB WE CE1 CE2 CE3OE

READ LOGIC

DQs DQP A DQPB DQPC DQPD

MEMORY

ARRAY E INPUT

REGISTER

BWC BWD

ADDRESS

REGISTER

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST LOGIC

A0'A1'D1

D0Q1

Q0A0A1

ADV/LD

CE

ADV/LD

CCLK CEN WRITE

DRIVERS

D A T A S T E E R I N G S E N S E A M P S

WRITE ADDRESS

REGISTER

A0, A1, A

O U T P U T B U F F E R S E ZZ SLEEP

CONTROL

CY7C1371S

Document Number: 001-43826 Rev. *F Page 3 of 29

Contents

Pin Configurations ...........................................................4 Pin Definitions ..................................................................6 Functional Overview ........................................................7 Single Read Accesses ................................................7 Burst Read Accesses ..................................................7 Single Write Accesses .................................................7 Burst Write Accesses ..................................................8 Sleep Mode .................................................................8 Interleaved Burst Address Table .................................8 Linear Burst Address Table .........................................8 ZZ Mode Electrical Characteristics ..............................8 Truth Table ........................................................................9 IEEE 1149.1 Serial Boundary Scan (JTAG) ..................10 Disabling the JTAG Feature ......................................10 Test Access Port (TAP) .............................................10 PERFORMING A TAP RESET ..................................10 TAP REGISTERS ......................................................10 TAP Instruction Set ...................................................10 TAP Controller State Diagram .......................................12 TAP Controller Block Diagram ......................................13 TAP Timing ......................................................................14 TAP AC Switching Characteristics ...............................14

3.3 V TAP AC Test Conditions .......................................15

3.3 V TAP AC Output Load Equivalent .........................15

2.5 V TAP AC Test Conditions .......................................15

2.5 V TAP AC Output Load Equivalent .........................15

TAP DC Electrical Characteristics

and Operating Conditions .............................................15Identification Register Definitions ................................16

Scan Register Sizes .......................................................16 Identification Codes .......................................................16 Boundary Scan Order ....................................................17 Maximum Ratings ...........................................................18 Operating Range .............................................................18 Electrical Characteristics ...............................................18 Capacitance ....................................................................19 Thermal Resistance ........................................................19 AC Test Loads and Waveforms .....................................19 Switching Characteristics ..............................................20 Switching Waveforms ....................................................21 Ordering Information ......................................................24 Ordering Code Definitions .........................................24 Package Diagrams ..........................................................25 Acronyms ........................................................................27 Document Conventions .................................................27 Units of Measure .......................................................27 Document History Page .................................................28 Sales, Solutions, and Legal Information ......................29 Worldwide Sales and Design Support .......................29 Products ....................................................................29 PSoC® Solutions ......................................................29 Cypress Developer Community .................................29 Technical Support .....................................................29

CY7C1371S

Document Number: 001-43826 Rev. *F Page 4 of 29

Pin Configurations

Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout A A A A A1 A0

NC/288M

NC/144M

V SS V DD

NC/36M

A A A A A A DQP B DQ B DQ B V DDQ V SS DQ B DQ B DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD DQ A DQ A V DDQ V SS DQ A DQ A DQ A DQ A V SS V DDQ DQ A DQ A DQP A DQP C DQ C DQ C V DDQ V SS DQ C DQ C DQ C DQ C V SS V DDQ DQ C DQ C NC V DD NC V SS DQ D DQ D V DDQ V SS DQ D DQ D DQ D DQ D V SS V DDQ DQ D DQ D DQP D A A CE 1 CE 2 BW D BW C BW B BW A CE 3 V DD V SS CLK

WECENOE

A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82

81AAADV/LD

ZZ MODE

NC/72M

CY7C1371S

BYTE A

BYTE B

BYTE D

BYTE C

A

CY7C1371S

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