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Motorola 6809 and

Hitachi 6309

ProgrammerÕs Reference

© 2009 by Darren Atkinson

- 2 -

A note about cycle counts

The MPU cycle counts listed throughout this document will sometimes show two different values separated by a slash. In these cases the first value indicates the number of cycles used on a 6809 or a 6309 CPU running in Emulation mode. The second value indicates the number of cycles used on a 6309 CPU only when running in Native mode.

Part I

Instruction Reference

- 4 - ABX

Add Accumulator B to Index Register X

X"

X + ACCB

The ABX instruction performs an unsigned addition of the contents of Accumulator B with the contents of Index Register X. The 16-bit result is placed into Index Register X.

None of the Condition Code flags are affected.

The ABX instruction is similar in function to the LEAX B,X instruction. A significant difference is that LEAX B,X treats B as a twos complement value (signed), whereas ABX treats B as unsigned. For example, if X were to contain 301B 16 and B were to contain FF 16 , then ABX would produce 311A 16 in X, whereas LEAX B,X would produce 301A
16 in X. Additionally, the ABX instruction does not affect any flags in the Condition Codes register, whereas the LEAX instruction does affect the Zero flag. One example of a situation where the ABX instruction may be used is when X contains the base address of a data structure or array and B contains an offset to a specific field or array element. In this scenario, ABX will modify X to point directly to the field or array element. The ABX instruction was included in the 6x09 instruction set for compatibility with the

6801 microprocessor.

SOURCE FORMADDRESSING MODEOPCODECYCLESBYTE COUNT

ABXINHERENT3A3 / 11

EFHINZVC

- 5 - ADC (8 Bit) Add Memory Byte plus Carry with Accumulator A or B r" r + (M) + C These instructions add the contents of a byte in memory plus the contents of the Carry flag with either Accumulator A or B. The 8-bit result is placed back into the specified accumulator. H The Half-Carry flag is set if a carry into bit 4 occurred; cleared otherwise. N The Negative flag is set equal to the new value of bit 7 of the accumulator. Z The Zero flag is set if the new accumulator value is zero; cleared otherwise. V The Overflow flag is set if an overflow occurred; cleared otherwise. C The Carry flag is set if a carry out of bit 7 occurred; cleared otherwise. The ADC instruction is most often used to perform addition of the subsequent bytes of a multi-byte addition. This allows the carry from a previous ADD or ADC instruction to be included when doing addition for the next higher-order byte. Since the 6x09 provides a 16-bit ADD instruction, it is not necessary to use the 8-bit ADD and ADC instructions for performing 16-bit addition.

See Also:

ADCD ADCR

EFHINZVC

ADCA8922994 / 32A94+2+B95 / 43

ADCBC922D94 / 32E94+2+F95 / 43

OP ~ #IMMEDIATEOP ~ #DIRECTOP ~ #INDEXEDOP ~ #EXTENDED

SOURCE

FORMS - 6 - ADCD

Add Memory Word plus Carry with Accumulator D

ACCD"

ACCD + (M:M+1) + C

The ADCD instruction adds the contents of a double-byte value in memory plus the value of the Carry flag with Accumulator D. The 16 bit result is placed back into Accumulator D. H The Half-Carry flag is not affected by the ADCD instruction. N The Negative flag is set equal to the new value of bit 15 of the accumulator. Z The Zero flag is set if the new Accumulator D value is zero; cleared otherwise. V The Overflow flag is set if an overflow occurred; cleared otherwise. C The Carry flag is set if a carry out of bit 15 occurred; cleared otherwise. The ADCD instruction is most often used to perform addition of subsequent words of a multi-byte addition. This allows the carry from a previous ADD or ADC instruction to be included when doing addition for the next higher-order word. The following instruction sequence is an example showing how 32-bit addition can be performed on a 6309 microprocessor:

LDQVAL1; Q = first 32-bit value

ADDWVAL2+2; Add lower 16 bits of second value

ADCDVAL2; Add upper 16 bits plus Carry

STQRESULT; Store 32-bit result

See Also:

ADC (8-bit) ADCR

EFHINZVC

6309 ONLY

ADCD10895 / 4410997 / 5310A97+ / 6+3+10B98 / 64

OP ~ #IMMEDIATEOP ~ #DIRECTOP ~ #INDEXEDOP ~ #EXTENDED

SOURCE

FORM - 7 - ADCR Add Source Register plus Carry to Destination Register r1" r1 + r0 + C The ADCR instruction adds the contents of a source register plus the contents of the Carry flag with the contents of a destination register. The result is placed into the destination register. H The Half-Carry flag is not affected by the ADCR instruction. N The Negative flag is set equal to the value of the result"s high-order bit. Z The Zero flag is set if the new value of the destination register is zero; cleared otherwise. V The Overflow flag is set if an overflow occurred; cleared otherwise. C The Carry flag is set if a carry out of the high-order bit occurred; cleared otherwise. Any of the 6309 registers except Q and MD may be specified as the source operand, destination operand or both; however specifying the PC register as either the source or destination produces undefined results. The ADCR instruction will perform either 8-bit or 16-bit addition according to the size of the destination register. When registers of different sizes are specified, the source will be promoted, demoted or substituted depending on the size of the destination and on which specific 8-bit register is involved. See "6309 Inter-Register Operations" on page 143 for further details. The Immediate operand for this instruction is a postbyte which uses the same format as that used by the TFR and EXG instructions. See the description of the TFR instruction for further details.

See Also:

ADC (8-bit) ADCD

SOURCE FORMADDRESSING MODEOPCODECYCLESBYTE COUNT

ADCR r0 r1

IMMEDIATE103143

EFHINZVC

6309 ONLY

- 8 - ADD (8 Bit)

Add Memory Byte to 8-Bit Accumulator

r" r + (M) ADDE and ADDF are available on 6309 only. These instructions add the contents of a byte in memory with one of the 8-bit accumulators (A,B,E,F). The 8-bit result is placed back into the specified accumulator. H The Half-Carry flag is set if a carry into bit 4 occurred; cleared otherwise. N The Negative flag is set equal to the new value of bit 7 of the accumulator. Z The Zero flag is set if the new accumulator value is zero; cleared otherwise. V The Overflow flag is set if an overflow occurred; cleared otherwise. C The Carry flag is set if a carry out of bit 7 occurred; cleared otherwise. The 8-bit ADD instructions are used for single-byte addition, and for addition of the least-significant byte in multi-byte additions. Since the 6x09 also provides a 16-bit ADD instruction, it is not necessary to use the 8-bit ADD and ADC instructions for performing

16-bit addition.

See Also:

ADD (16-bit) ADDR

EFHINZVC

ADDA8B229B4 / 32AB4+2+BB5 / 43

ADDBCB22DB4 / 32EB4+2+FB5 / 43

ADDE118B33119B5 / 4311AB5+3+11BB6 / 54

ADDF11CB3311DB5 / 4311EB5+3+11FB6 / 54

OP ~ #IMMEDIATEOP ~ #DIRECTOP ~ #INDEXEDOP ~ #EXTENDED

SOURCE

FORMS - 9 - ADD (16 Bit)

Add Memory Word to 16-Bit Accumulator

r" r + (M:M+1) ADDW is available on 6309 only. These instructions add the contents of a double-byte value in memory with one of the 16- bit accumulators (D,W). The 16-bit result is placed back into the specified accumulator. H The Half-Carry flag is not affected by these instructions. N The Negative flag is set equal to the new value of bit 15 of the accumulator. Z The Zero flag is set if the new accumulator value is zero; cleared otherwise. V The Overflow flag is set if an overflow occurred; cleared otherwise. C The Carry flag is set if a carry out of bit 15 occurred; cleared otherwise. The 16-bit ADD instructions are used for double-byte addition, and for addition of the least-significant word of multi-byte additions. See the description of the ADCD instruction for an example of how 32-bit addition can be performed on a 6309 processor.

See Also:

ADD (8-bit) ADDR

EFHINZVC

ADDDC34 / 33D36 / 42E36+ / 5+2+F37 / 53

ADDW108B5 / 44109B7 / 5310AB7+ / 6+3+10BB8 / 64

OP ~ #IMMEDIATEOP ~ #DIRECTOP ~ #INDEXEDOP ~ #EXTENDED

SOURCE

FORMS - 10 - ADDR

Add Source Register to Destination Register

r1" r1 + r0 The ADDR instruction adds the contents of a source register with the contents of a destination register. The result is placed into the destination register. H The Half-Carry flag is not affected by the ADDR instruction. N The Negative flag is set equal to the value of the result"s high-order bit. Z The Zero flag is set if the new value of the destination register is zero; cleared otherwise. V The Overflow flag is set if an overflow occurred; cleared otherwise. C The Carry flag is set if a carry out of the high-order bit occurred; cleared otherwise. Any of the 6309 registers except Q and MD may be specified as the source operand, destination operand or both; however specifying the PC register as either the source or destination produces undefined results. The ADDR instruction will perform either 8-bit or 16-bit addition according to the size of the destination register. When registers of different sizes are specified, the source will be promoted, demoted or substituted depending on the size of the destination and on which specific 8-bit register is involved. See "6309 Inter-Register Operations" on page 143 for further details. A

Load Effective Address

instruction which adds one of the 16-bit accumulators to an index register (such as LEAX D,X) could be replaced by an ADDR instruction (ADDR D,X) in order to save 4 cycles (2 cycles in Native Mode). However, since more Condition Code flags are affected by the ADDR instruction, you should avoid this optimization if preservation of the affected flags is desired. The Immediate operand for this instruction is a postbyte which uses the same format as that used by the TFR and EXG instructions. See the description of the TFR instruction for further details.

See Also:

ADD (8-bit) ADD (16-bit)

SOURCE FORMADDRESSING MODEOPCODECYCLESBYTE COUNT

ADDR r0 r1

IMMEDIATE103043

EFHINZVC

6309 ONLY

- 11 - AIM

Logical AND of Immediate Value with Memory Byte

M" (M) AND IMM The AIM instruction logically ANDs the contents of a byte in memory with an 8-bit immediate value. The resulting value is placed back into the designated memory location. N The Negative flag is set equal to the new value of bit 7 of the memory byte. Z The Zero flag is set if the new value of the memory byte is zero; cleared otherwise. V

The Overflow flag is cleared by this instruction.

C The Carry flag is not affected by this instruction. AIM is one of the more useful additions to the 6309 instruction set. It takes three separate instructions to perform the same operation on a 6809: 6809
(6 instruction bytes; 12 cycles)

LDA#$3F

ANDA4,U

STA4,U

6309
(3 instruction bytes; 8 cycles)

AIM#$3F;4,U

Note that the assembler syntax used for the AIM operand is non-typical. Some assemblers may require a comma (,) rather than a semicolon (;) between the immediate operand and the address operand. The object code format for the AIM instruction is:

See Also:

AND EIM OIM TIM

EFHINZVC

0

OPCODEIMMED VALUEADDRESS / INDEX BYTE(S)

6309 ONLY

AIM # i8 ; EA 0263627+3+7274

OP ~ #IMMEDIATEOP ~ #DIRECTOP ~ #INDEXEDOP ~ #EXTENDED

SOURCE

FORM - 12 - AND (8 Bit)

Logically AND Memory Byte with Accumulator A or B

r" r AND (M) These instructions logically AND the contents of a byte in memory with either Accumulator A or B. The 8-bit result is then placed in the specified accumulator. N The Negative flag is set equal to the new value of bit 7 of the accumulator. Z The Zero flag is set if the new value of the accumulator is zero; cleared otherwise. V

The Overflow flag is cleared by this instruction.

C The Carry flag is not affected by this instruction. The AND instructions are commonly used for clearing bits and for testing bits. Consider the following examples:

ANDA#%11101111;Clears bit 4 in A

ANDA#%00000100;Sets Z flag if bit 2 is not set

When testing bits, it is often preferable to use the BIT instructions instead, since they perform the same logical AND operation without modifying the contents of the accumulator.

See Also:

AIM, ANDCC, ANDD

ANDR BAND BIAND BIT

EFHINZVC

0

ANDA8422944 / 32A44+2+B45 / 43

ANDBC422D44 / 32E44+2+F45 / 43

OP ~ #IMMEDIATEOP ~ #DIRECTOP ~ #INDEXEDOP ~ #EXTENDED

SOURCE

FORMS - 13 - ANDCC Logically AND Immediate Value with the CC Register CC"

CC AND IMM

This instruction logically ANDs the contents of the Condition Codes register with the immediate byte specified in the instruction. The result is placed back into the Condition

Codes register.

The ANDCC instruction provides a method to clear specific flags in the Condition Codes register. All flags that correspond to "0" bits in the immediate operand are cleared, while those corresponding with "1"s are left unchanged.

The bit numbers for each flag are shown below:

One of the more common uses for the ANDCC instruction is to clear the IRQ and FIRQ Interrupt Masks (I and F) at the completion of a routine that runs with interrupts disabled.

This is accomplished by executing:

ANDCC#$AF; Clear bits 4 and 6 in CC

Some assemblers will accept a comma-delimited list of the bit names to be cleared as an alternative to the immediate expression. For instance, the example above might also be written as:

ANDCCI,F; Clear bits 4 and 6 in CC

This syntax is generally discouraged due to the confusion it can create as to whether it means clear the I and F bits, or clear all bits except I and F.

More examples:

ANDCC#$FE; Clear the Carry flag

ANDCC#1; Clear all flags except Carry

See Also:

AND (8-bit) ANDD ANDR CWAI ORCC

SOURCE FORMADDRESSING MODEOPCODECYCLESBYTE COUNT

ANDCC #i8

IMMEDIATE1C32

76543210

EFHINZVC

- 14 - ANDD

Logically AND Memory Word with Accumulator D

ACCD"

ACCD AND (M:M+1)

The ANDD instruction logically ANDs the contents of a double-byte value in memory with the contents of Accumulator D. The 16-bit result is placed back into Accumulator D. N The Negative flag is set equal to the new value of bit 15 of Accumulator D. Z The Zero flag is set if the new value of the Accumulator D is zero; cleared otherwise. V

The Overflow flag is cleared by this instruction.

C The Carry flag is not affected by this instruction. One use for the ANDD instruction is to truncate bits of an address value. For example:

ANDD#$E000;Convert address to that of its 8K page

For testing bits, it is often preferable to use the BITDquotesdbs_dbs11.pdfusesText_17

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