[PDF] Asynchonous Communications Element datasheet (Rev. E)

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TL16C554A, TL16C554AI

ASYNCHRONOUS-COMMUNICATIONS ELEMENT

SLLS509E - AUGUST 2001 - REVISED JUNE 2010

1

POST OFFICE BOX 655303 € DALLAS, TEXAS 75265

?Integrated Asynchronous-Communications

Element

?Consists of Four Improved TL16C550CACEs Plus Steering Logic

?In FIFO Mode, Each ACE Transmitter andReceiver Is Buffered With 16-Byte FIFO toReduce the Number of Interrupts to CPU

?In TL16C450 Mode, Hold and ShiftRegisters Eliminate Need for PreciseSynchronization Between the CPU andSerial Data

?Up to 16-MHz Clock Rate for up to 1-MbaudOperation with V CC = 3.3 V and 5 V ?Programmable Baud-Rate GeneratorsWhich Allow Division of Any InputReference Clock by 1 to (2 16 ??1) and

Generate an Internal 16 × Clock

?Adds or Deletes Standard Asynchronous

Communication Bits (Start, Stop, and

Parity) to or From the Serial-Data Stream

?Independently Controlled Transmit,Receive, Line Status, and Data SetInterrupts ?5-V and 3.3-V Operation

?Fully Programmable Serial InterfaceCharacteristics: 5-, 6-, 7-, or 8-Bit Characters Even-, Odd-, or No-Parity Bit 1-, 1 1/2-, or 2-Stop Bit Generation Baud Generation (DC to 1-Mbit Per

Second)

?False Start Bit Detection ?Complete Status Reporting Capabilities ?Line Break Generation and Detection ?Internal Diagnostic Capabilities: Loopback Controls for Communications

Link Fault Isolation

Break, Parity, Overrun, Framing Error

Simulation

?Fully Prioritized Interrupt System Controls ?Modem Control Functions (CTS, RTS, DSR, DTR , RI, and DCD) ?3-State Outputs Provide TTL DriveCapabilities for Bidirectional Data Bus andControl Bus ?Programmable Auto-RTS and Auto-CTS ?CTS Controls Transmitter in Auto-CTS Mode, ?RCV FIFO Contents and Threshold ControlRTS in Auto-RTS Mode, description The TL16C554A is an enhanced quadruple version of the TL16C550C asynchronous-communications element

(ACE). Each channel performs serial-to-parallel conversion on data characters received from peripheral

devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete

status of each channel of the quadruple ACE can be read by the CPU at any time during operation. The

information obtained includes the type and condition of the operation performed and any error conditions

encountered.

The TL16C554A quadruple ACE can be placed in an alternate FIFO mode, which activates the internal FIFOs

to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in both receive and

transmit modes. In the FIFO mode of operation, there is a selectable autoflow control feature that can

significantly reduce software overhead and increase system efficiency by automatically controlling serial-data

flow using RTS output and CTS input signals. All logic is on the chip to minimize system overhead and maximize

system efficiency. Two terminal functions allow signaling of direct-memory access (DMA) transfers. Each ACE

includes a programmable baud-rate generator that can divide the timing reference clock input by a divisor

between 1 and 2 16 1.

The TL16C554A is available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package, 64-pin plastic quad

flatpack (PQFP) PM package and in an 80-pin (TQFP) PN package.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily includetesting of all parameters.Copyright 2010, Texas Instruments Incorporated

TL16C554A, TL16C554AI

ASYNCHRONOUS-COMMUNICATIONS ELEMENT

SLLS509E - AUGUST 2001 - REVISED JUNE 2010

2POST OFFICE BOX 655303 € DALLAS, TEXAS 75265

28 29
DSRD CTSD DTRD GND RTSD INTD CSD TXD IOR TXC CSC INTC RTSC V CC DTRC CTSC DSRC 60
59
58
57
56
55
54
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51
50
49
48
47
46
45
44
3010
11 12 13 14 15 16 17 18 19 20 21
22
23
24
25
26
DSRA CTSA DTRA V CC RTSA INTA CSA TXA IOW TXB CSB INTB RTSB GND DTRB CTSB DSRB

31 32 33 34FN PACKAGE

(TOP VIEW) D2 D1

87 65493

RXA GND D7 D6 D5 D4 D3 XTAL2 RESET RXRDY

TXRDYRXB

NC A2 A1 A0 XTAL1

168672

35 36 37 38 3966 65

27
DCDB D0 INTN

64 63 62 61

40 41 42 43

GND RXC RIC

DCDCRXD

RID

DCDDDCDA

RIA V CC RIB V CC

NC No internal connection

TL16C554A, TL16C554AI

ASYNCHRONOUS-COMMUNICATIONS ELEMENT

SLLS509E - AUGUST 2001 - REVISED JUNE 2010

3POST OFFICE BOX 655303 € DALLAS, TEXAS 75265

23
DSRC DCDC RIC RXC GND RESET XTAL2 XTAL1 A0 A1 A2 V CC RXB RIB DCDB DSRB 32
31
30
29
28
27
26
25
24
23
22
21
20 19 18 17 449
50
51
52
53
54
55
56
57
58
59
60
61
62
63

64DCDD

RID RXD V CC D0 D1 D2 D3 D4 D5 D6 D7 GND RXA RIA DCDA

5678PM PACKAGE

(TOP VIEW) TXC CSC

47 46 45 44 4348 42

DTRD GND RTSD INTD CSD TXD IOR TXB CSB INTB

RTSBDTRA

RTSA INTA CSA TXA IOW

40 39 3841

91011121337 36

1 DSRA INTC RTSC

35 34 33

14 15 16

GND DTRB

CTSBDTRC

CTSCDSRD

CTSD V CC CTSA V CC

NC No internal connection

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