[PDF] [PDF] IE1204 Digital Design F12: Asynchronous Sequential Circuits (Part 1)

[PDF] Asynchronous Sequential Circuits

Asynchronous sequential circuits have state that is not synchronized with a clock Like the synchronous sequential circuits we have studied up to this point they are realized by adding state feedback to combinational logic that imple- ments a next-state function

[PDF] Chapter 9 Asynchronous Sequential Logic Outline

Asynchronous Sequential Circuits ▫ Analysis Procedure ▫ Circuits with Latches ▫ Design Procedure ▫ Reduction of State and Flow Tables ▫ Race- Free 

Appendix 1 Asynchronous Sequential Logic Design

A block diagram of a sequential circuit or machine is shown in figure Al l Inputs = == Combinational I==:> Outputs Logic Memory Internal States ~- 

[PDF] IE1204 Digital Design F12: Asynchronous Sequential Circuits (Part 1)

gates and summarize their delays to a single block with delay Δ Asynchronous sequential circuit: SR-latch with NOR gates IE1204 Digital Design, Autumn2016

[PDF] Asynchronous Sequential Circuits

From a logic diagram, Boolean expressions are written and then transferred into tabular form An example of an asynchronous sequential circuit is shown below :

[PDF] Design of asynchronous esign of asynchronous sequential circuits

There are two distinct models by which a synchronous sequential logic circuit can be designed In Mealy Model, the output is derived from present state as well as 

[PDF] Asynchronous Sequential Circuits Design - CCS University

Asynchronous sequential circuits do not use clock signals as synchronous circuits do Instead, the circuit is driven by the pulses of the inputs which means the state 

[PDF] Asynchronous Circuits - Department of Electronics

asynchronous circuits and brie y explain some asynchronous design ments, instead of in latches or ip- ops, as synchronous sequential circuits do The design

[PDF] Synchronous Sequential Circuit

Have better performance but hard to design due to timing problems Why Asynchronous Circuits? ✓ Accelerate the speed of the machine (no need to wait for the 

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IE1204 Digital Design

F12: Asynchronous

Sequential Circuits

(Part 1)

Masoumeh(Azin) Ebrahimi (masebr@kth.se)

Elena Dubrova (dubrova@kth.se)

KTH / ICT / ES

BV pp. 584-640This lecture

IE1204 Digital Design, Autumn2016

Asynchronous Sequential

Machines

An asynchronous sequential machine is

a sequential machine without flip-flops

Asynchronous sequential machines are

constructed by analyzing combinational logic circuits with feedback Assumption: Only one signal in acircuit can change its value at any time

IE1204 Digital Design, Autumn2016

Golden rule

IE1204 Digital Design, Autumn2016

Asynchronous state machines

Asynchronous state machines are used

when it is necessary to keep the information about a state, but no clock is available - All flip-flops and latches are asynchronous state machines - Useful to synchronize events in situations where metastability is/can be a problem

IE1204 Digital Design, Autumn2016

To analyze the behavior of an

asynchronous circuit, we use ideal gates and summarize their delays to a single block with delay ǻAsynchronous sequential circuit:

SR-latch with NOR gates

IE1204 Digital Design, Autumn2016

R S

QYyDelayIdeal gates

(Delay = 0)Q aR

SSR-latch

By using a delay block, we can treat

- y as the current state - Y as the next stateAnalysis of a sequential asynchronous circuit

IE1204 Digital Design, Autumn2016

R S QYy

Thus, we can produce a state table where the

next state Y depends on the inputs and the current state yState table

IE1204 Digital Design, Autumn2016

R S QY y)(ySRY

State table

IE1204 Digital Design, Autumn2016

)(ySRYPresent

Nextstate

state

SR= 0001 1011

y YYYY

0001011010

ySRYRSyFrom statefunction to truth tableNote: BV usesthisbinary code

Since we do not have flip-flops, but only

combinational circuits, a state change can cause additional state changes

A state is

- stable if Y(t) = y(t + ǻ) - unstable if Y(t) y(t + ǻ)Stable states

IE1204 Digital Design, Autumn2016

Present

Nextstate

state

SR= 0001 1011

y YYYY

0001011010

yYstable

Stable states (next state = present state) are

circledExcitation table

IE1204 Digital Design, Autumn2016

Present

Nextstate

state

SR= 0001 1011

y YYYY

0001011010R

S QYy 00 0 10R S QYy 10 0 01

When dealing with asynchronous

sequential circuits, a different terminology is used - The state table calledflow table - The state-assigned state table is called excitation tableTerminology

IE1204 Digital Design, Autumn2016

Flow table (Moore)

IE1204 Digital Design, Autumn2016

Present

NextstateOutput

state

SR= 0001 1011Q

AAABA0

BBABA1

1000

11010010

A0 B1

1101SR

Flow Table (Mealy)

IE1204 Digital Design, Autumn2016

Present

NextstateOutput,Q

state

SR = 0001 1011 00 01 1011

AAABA000

BBABA11-

-10/1

00/111/0

01/000/010 /-

AB 01-

11-SR/ QDo not care ('-') has been chosen for output decoder since output changes

directly after the state transition (basic implementation)

Asynchronous Moore compatible

IE1204 Digital Design, Autumn2016

Asynchronous sequential circuits have similar

structure as synchronous sequential circuits

Instead of flip-flops one have a "delay block"

R S QYy 10 01 0

Asynchronous Mealy compatible

IE1204 Digital Design, Autumn2016

Asynchronous sequential circuits have similar

structure as synchronous sequential circuits

Instead of flip-flops one have a "delay block"

Analysis of Asynchronous Circuits

The analysis is done using the following steps:

1)Replace the feedbacks in the circuit with a

delay element.The input of the delay element represents the next state Y while the output y represents the current state.

2) Find out thenext-state and output expressions

3) Set up the correspondingexcitation table

4) Create aflow tableand replace the encoded

states with symbolic states

5) Draw astate diagramif necessary

IE1204 Digital Design, Autumn2016

D-latch state function

IE1204 Digital Design, Autumn2016

Q 1D C1QD CQ D CYy CyCDY

Master-slave D flip-flop is designed

using two D-latchesExample

Master-slave D flip-flop

IE1204 Digital Design, Autumn2016

D ClkQQ D CQ ysymMasterSlaveQ D ClkQQ s ssmm yQCyDCYyCCDY

The equations for the next state:

From these equations, we can directly

deduce excitation tableExcitation table

IE1204 Digital Design, Autumn2016

Present

Nextstate

state

CD= 0001 1011Output

y mys YmYsQ

0000 00 00100

0100 00 01111

1011 11 00 100

1111 11 01 111s

ssmm yQCyDCYyCCDY

Excitation table

We define four states S1, S2, S3, S4

and get the following flow tableFlow table

IE1204 Digital Design, Autumn2016

Present

NextstateOutput

state

CD= 00 01 1011Q

S1S1 S1 S1S30

S2S1 S1 S2S41

S3S4 S4 S1 S30

S4S4S4S2S41Present

Nextstate

stateCD= 00 01 1011Output y mys YmYsQ

0000 00 00100

0100 00 01111

1011 11 00 100

11111101111

Excitation table

Flow table

Remember: Only one input can be

changed simultaneously

Thus, some transitions never occur!Flow table

IE1204 Digital Design, Autumn2016

Present

NextstateOutput

state

CD= 0001 1011Q

S1S1 S1 S1S30

S2S1 S1 S2S41

S3S4 S4 S1 S30

S4S4S4S2S41

State S3

- The only stable state is S3 with input combination 11 - Only one input can be changed => possible transitions are (11 =>

01, 11 => 10)

These transitions originate in S3!

The input combination 00 in S3 is not possible!

The input combination 00 is set to don't care!Flow table (Impossible transitions)

IE1204 Digital Design, Autumn2016

Present

NextstateOutput

state

CD= 0001 1011Q

S1S1S1S1S30

S2S1 S1 S2S41

S3S4 S4 S1 S30

S4S4S4S2S41

State S2

- The only stable state is S2 with input combination 10 - Only one entry can be changed => possible transitions are (10 =>

11, 10 => 00)

These transitions originate in S2!

The input combination 01 in S2 is not possible!

The input combination 01 is set to don't care!Flow table (Impossible transitions)

IE1204 Digital Design, Autumn2016

Present

NextstateOutput

state

CD= 00 01 1011Q

S1S1 S1 S1S30

S2S1S2S41

S3S4 S1 S30

S4S4S4S2S41S1

State Diagram

Master-slave D flip-flop

IE1204 Digital Design, Autumn2016

x10x 1011
S21

S411011

x00x11 S10 S3010

0x0xCD

Present

NextstateOutput

state

CD= 00 01 1011Q

S1S1 S1 S1S30

S2S1S2S41

S3S4 S1 S30

S4S4S4S2S41-

-Flow table

State diagram

Synthesis of asynchronous

circuits

The synthesis is carried out using the following

steps:

1)Create astate diagramaccording to the functional

description

2) Create aflow tableandreduce the number of states

if possible

3) Assign codes to the states and createexcitations table

4)Determine expressions(transfer functions) for the

next state and outputs

5)Construct a circuitthat implements the above

expressionsquotesdbs_dbs17.pdfusesText_23