Design compiler all_fanout

In Design Compiler you can use the command all_high_fanout -nets to obtain a collection of nets that has a fanout value bigger than high_fanout_net_threshold variable, which you can review using the command report_app_var high_fanout_net_threshold.
A specific threshold N can also defined using the command:.

Design Compiler computes the delays of high-fanout nets with a simpler model to delimit the computation effort.
That can reduce the accuracy of timing analysis on the relevant nets, which mostly carry reset or scan signals.
If timing constraints have enough margins or delay of the net is not so critical, the warning can be ignored.

(TIM-134) - Stack Overflow Warning:

2) If the high fanout is real and you can tolerate the slow timings as a result, then increase the fanout limit in your synthesis tool. 3) If the high fanout is real and you can NOT tolerate the slow timings, then check that the tool is replicating the signal enough times to reduce the fanout and improve timings.