Design compiler change net name

Jun 8, 2020design compiler change net name. I think you need to define the naming rule for "simple_names" before you can use it in change naming command :eek: Dec 4 why design compiler change my FF output naming?Preserving net naming in Synthesis using DC | Forum for ElectronicsCreate a case insensitive netlist from verilog using DC[SOLVED] - Get all nets without the input nets in design compilerMore results from www.edaboard.com

How do I change a net name?

Pick a net and enter a new net name in the pop-up form that appears: The form, when it appears, is pre-populated with the original net name.
If you accidentally choose the wrong net, a quick tap of the enter key will close the form and nothing will change.
But, once you verify the right net is active, type in the new name.

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