Design compiler path is unconstrained

  • What happens if the path is unconstrained in VLSI?

    Note: If timing paths are unconstrained, the check_timing command only reports the unconstrained endpoints, not the unconstrained startpoints..

  • Answer: The "unconstrained endpoints" warning message identifies timing path endpoints that are not constrained. for maximum delay (setup) checks.
Nov 2, 2014As you haven't created any constraints for output pins (or as a matter of fact for input pins either) you get an unconstrained path. I would  How to find unconstrained paths in a design? - Forum for ElectronicsUnconstrained PAth in a fulladder design - DC - Forum for Electronics[SOLVED] - Synopsys DC not constrainted endpointsHelp in Synthesis using DC compiler - Forum for ElectronicsMore results from www.edaboard.com
Nov 2, 2014Hi Friends when I am trying the command "report_timing", I am not getting Slack, but I am getting path is unconstrained can you tell me How  How to find unconstrained paths in a design? - Forum for ElectronicsUnconstrained PAth in a fulladder design - DC - Forum for Electronics[SOLVED] - Synopsys DC not constrainted endpointsHelp in Synthesis using DC compiler - Forum for ElectronicsMore results from www.edaboard.com
Nov 2, 2014Hi Friends when I am trying the command "report_timing", I am not getting Slack, but I am getting path is unconstrainedHow to find unconstrained paths in a design? - Forum for ElectronicsUnconstrained PAth in a fulladder design - DC - Forum for Electronics[SOLVED] - Synopsys DC not constrainted endpointsHelp in Synthesis using DC compiler - Forum for ElectronicsMore results from www.edaboard.com

Can a compiler see a path that doesn't end in a return?

The compiler isn't kidding; it really can see paths through your code that don't end in a return.
You can trace them too. follow your true case. it can reach break, exit the switch and then have no return statement before it hits the end of the method.

How to generate a report that details all unconstrained paths?

With the Timing Analyzer command report_ucp, you can generate a report that details all unconstrained paths in your design.
Unconstrained paths are paths without any timing constraints specified to them, i. e. set_input_delay, create_clock, etc.
The report details the type of unconstrained paths:

  • clocks
  • input ports
  • outputs ports.

    • What does path is unconstrained mean?

    After you read that, you will no longer ask "do I need to increase clock?" when you are presented a "Path is unconstrained" message.
    This is the output of a register (flip-flop).
    As you haven't created any constraints for output pins (or as a matter of fact for input pins either) you get an unconstrained path.

    Why does design_compiler synthesis not work?

    If you have setup a clock that is FAR to fast for your design, the design_compiler will synthesize something, but it won't have met the constraint you have setup.
    Or if you set a fanin/fanout load that is unreasonable, the same will occur.
    You need to check the results of the synthesis by checking the synthesis reports.


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