Design compiler get_nets

  • What is DC shell?

    Design Compiler (DC) from Synopsys and RTL Compiler from Cadence are the tools widely used for synthesis.
    Synthesis is described as translation plus logic optimization plus mapping.
    In terms of the Synopsys tools, translation is performed during reading the files..

Jun 17, 2016Hi guys, Exist any solution to use the command get_nets to obtain all nets without the input nets ? Regards, DustHerder.

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