Design compiler timing loop

Is timing analysis a problem in RTL?

I'm not 100% sure this is your problem, but it certainly is a problem in your RTL.
Timing analysis is based on events, in the sense that constraints must be created such that data is generated and sampled and to allow Design Compiler (DC) to analyse timing paths between the various event points.

Why is timing analysis based on events?

Timing analysis is based on events, in the sense that constraints must be created such that data is generated and sampled and to allow Design Compiler (DC) to analyse timing paths between the various event points.
Typically a block will sample the input data before using it and the output of the internal combinatorial logic is also sampled.

Attempt to compromise a cryptosystem by analyzing the time taken to execute cryptographic algorithms


In cryptography, a timing attack is a side-channel attack in which the attacker attempts to compromise a cryptosystem by analyzing the time taken to execute cryptographic algorithms.
Every logical operation in a computer takes time to execute, and the time can differ based on the input; with precise measurements of the time for each operation, an attacker can work backwards to the input.
Finding secrets through timing information may be significantly easier than using cryptanalysis of known plaintext, ciphertext pairs.
Sometimes timing information is combined with cryptanalysis to increase the rate of information leakage.

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