Microprocessors and Microcontrollers lab LIST OF EXPERIMENTS S
29 janv. 2020 (d) Division of 2 - 8 bit numbers using microcontroller 8051 ... an assembly language program for 16 bit division in 8085 microprocessor.
MPMC lab manual
TSCR8051 8051 RISC Microcontroller High-Speed 8051
8 juin 2010 priority levels o 15-bit programmable watchdog timer o Core 8-bit arithmetic logic unit and 16-bit multiplication division unit.
tscr
Cast C8051 Core Data Sheet
8-bit Arithmetic-Logic Unit with. 8-bit multiplication and division. Instruction decoder. C8051. Four 8-bit Input / Output ports. Two 16-bit Timer/Counters.
cast c
SEMESTER -VI EC334 MICROCONTROLLER LAB
Addition / subtraction / multiplication / division of 8/16 bit data. 8051 microcontroller has an internal program of 4K size and if needed an external.
EC Microcontrollers Lab manual final
Programs for 16 bit arithmetic operations of 8086 (using various
D. WORD BY BYTE DIVISION. AX= 390F & SI=0003 ; D 0000 0004 44 04 45 0F 39. PROGRAMS (using indirect register addressing mode):. E. 16 BIT ADDITION.
mp and mc lab manual eee
Exp No.1: Programs for 16 bit arithmetic operations for 8086
d) Division: I) 16 bit division: AIM: - To write an assembly language program for multiplication of two 16-bit numbers. APPARATUS: 1. 8086 microprocessor
mpmc ECE manual
MICROCONTROLLERS LAB – 18ECL47 MANUAL
MICROCONTROLLER LAB MANUAL. (18ECL47) 1.3 LARGEST/SMALLEST ELEMENT IN AN ARRAY USING 8051 . ... 3 WRITE AN ALP TO PERFORM DIVISION (16-bit by 16-bit) .
mc
Digital Core DP8051XP Data Sheet
DP8051XP. Pipelined High Performance. 8-bit Microcontroller ver 3.10. OVERVIEW data and program buses are separated and ... Division - 16bit / 16bit.
dp xp ds
CS6412-Microprocessor And Microcontroller Laboratory
A/D and D/A interface and Waveform Generation 8051. Experiments using kits and MASM To write an assembly language program to perform division two 16 bit.
CS MICROPROCESSOR AND MICROCONTROLLER LABORATORY
CS6412-Microprocessor And Microcontroller Laboratory
A/D and D/A interface and Waveform Generation 8051. Experiments using kits and MASM To write an assembly language program to perform division two 16 bit.
CS MICROPROCESSOR AND MICROCONTROLLER LABORATORY
Draft TSCR8051
8051 RISC Microcontroller High-Speed, 8051-Compatible,
With SRAM and Extended Functions
Rev. 0.1 - June 8, 2010 Page 1 of 60 © Tezzaron Semiconductor Corporation1. Description
The TSCR8051 8-bit microcontroller is software compatible with the millions of devices that have been produced since
Intel®
introduced the 8051 line in 1980. It executes all ASM51 instructions and uses the same instruction set as the 8031.
Its Reduced Instruction Set Computer (RISC) core executes many of its instructions in a single clock cycle, providing a
significant speed advantage over traditional 8051 devices that execute an instruction every twelve clock cycles. With
clock speeds of up to 200 MHz, this device is an 8051 performance leader.The TSCR8051 features 128KBKBytes of partitionable Data and Program memory and extended 32-bit capabilities
including an IEEE 754-compliant floating-point coprocessor with comparator, a multiply/divide unit, a population counter,
and a leading-zero counter. 2. FeaturesIndustry standard 8051 / 8031 software compatible
RISC architecture with up to x12 speed advantage / MHz over traditional 8051 family devicesFour speed grades: 100, 150, 180, and 200 MHz
128KB of additional high-speed SRAM memory
IEEE 754-compliant floating point coprocessor for full arithmetic capabilities - up to 100 MFlops Extended 32-bit computing functions including population counter, leading zero counter, and floating-point comparatorDual data pointers for fast data block moves
Full 8051-compatible architecture including:
o Four 8-bit bi-directional ports o 256 Bytes of "Scratch Pad" memory o Three 16-bit timer/counters o Interrupt controller with 12 interrupt sources and 4 priority levels o 15-bit programmable watchdog timer o Core 8-bit arithmetic logic unit and 16-bit multiplication division unit o Two full-duplex serial ports o Four capture/compare units to generate pulse width modulated signals o Special Function Register (SFR) interface, serving up to 50 SFR devices 3. Part NumberingOptions Marking
Packages:
44 PLCC xxxxx
68 PLCC xxxxx
100 TQFP xxxxx
Operating Temperature:
Standard, 0º to 70º C S
Extended (planned) E
Speed Grade:
66 MHz -06
100 MHz -10
150 MHz -15
180 MHz -18
200 MHz -20
Part number example: TSCxxxxxPS-06 4. Operating Voltages V DDQ, V DDQF = 3.3 ± .3 VDC V DD = 1.8 ± .2 VDC DraftTSCR8051
Rev. 0.1 - June 8, 2010 Page 2 of 60 © Tezzaron Semiconductor CorporationFigure 1: Block Diagram
SRAM DataMemoryProgram
Memory
Extended
Computing
FunctionsFloating
PointUnitSPI
Memory
LoaderMemory
ControlTimers
Interrupt
Service
Register
Bidirectional
DataPorts256 Byte
Scratch Pad
Memory
Scratch Pad /
SFRControl
ALUMultiply
Divide
UnitSerial
PortsPulse Width
Modulator
UnitWatchdog
TimerRISC 8051 Microcontroller Core
Core Internal SFR Bus
TSCR8051 Functions
SFR Bus
5. Table of Contents
1. Description ......................................................... 1
2. Features ............................................................. 1
3. Part Numbering .................................................. 1
4. Operating Voltages ............................................ 1
5. Table of Contents ............................................... 2
6. Table of Figures ................................................. 2
7. Table of Tables .................................................. 3
8. Block Diagram .................................................... 4
9. Pin-Out ............................................................... 4
10. Special Function Registers ................................ 9
11. Memory ............................................................ 32
12. Instruction Set .................................................. 34
13. External SFR Timing ........................................ 42
14. Hardware Overview .......................................... 43
15. Core Engine ..................................................... 43
16. Multiplication / Division Unit (MDU) ................. 43
17. Timers .............................................................. 45
18. Serial Ports ...................................................... 51
19. Interrupts .......................................................... 54
20. Floating Point Unit (FPU) ................................. 57
21. Extended Computing Functions....................... 57
22. SPI Memory Loader ......................................... 58
23. Reset Control ................................................... 58
24. Power Management ......................................... 58
25. Device Specifications ....................................... 59
26. Package Dimensions ....................................... 59
27. Document History ............................................ 60
6. Table of Figures
Figure 1: Block Diagram ......................................................................................................................................................... 2
Figure 2: 44 PPLC, Top View .................................................................................................................................................. 4
Advance Data
TSCR8051
Special Function Register Descriptions (Continued) Rev. 0.1 - June 8, 2010 Page 3 of 60 © Tezzaron Semiconductor CorporationFigure 3 - Scratch Pad Memory ........................................................................................................................................... 32
Figure 4 - SRAM Memory Layout ......................................................................................................................................... 33
Figure 5 - External Use of Special Function Register Bus (read) ........................................................................................ 42
Figure 6 - External Use of Special Function Register Bus (write) ........................................................................................ 42
Figure 7 - Timer/Counter 1 in Mode 0 .................................................................................................................................. 46
Figure 8 - Timer/Counter 1 in Mode 2 .................................................................................................................................. 47
Figure 9 - Timer/Counter 0 in Mode 3 .................................................................................................................................. 47
Figure 10 - Timer 2 as Gated Timer: Prescaler Select = 1, Reload Mode = 1 ..................................................................... 49
Figure 11 - Timer 2 as Counter: Capture Mode = 0 (using CC3) ......................................................................................... 50
Figure 12 - Timer 2: Reload Mode = 0, Compare Mode = 0 (using CC2) ............................................................................ 50
Figure 13 - Receive Timing, Mode 0 .................................................................................................................................... 52
Figure 14 - Receive Timing, Modes 1 and B ........................................................................................................................ 53
Figure 15 - Receive Timing, Modes 2, 3, and A ................................................................................................................... 53
Figure 16 - Transmit Timing, Mode 0 ................................................................................................................................... 53
Figure 17 - Transmit Timing, Modes 1 and B ....................................................................................................................... 53
Figure 18 - Transmit Timing, Modes 2, 3, and A .................................................................................................................. 54
Figure 19 - Interrupt Processing ........................................................................................................................................... 56
7. Table of Tables
DraftTSCR8051
8051 RISC Microcontroller High-Speed, 8051-Compatible,
With SRAM and Extended Functions
Rev. 0.1 - June 8, 2010 Page 1 of 60 © Tezzaron Semiconductor Corporation1. Description
The TSCR8051 8-bit microcontroller is software compatible with the millions of devices that have been produced since
Intel®
introduced the 8051 line in 1980. It executes all ASM51 instructions and uses the same instruction set as the 8031.
Its Reduced Instruction Set Computer (RISC) core executes many of its instructions in a single clock cycle, providing a
significant speed advantage over traditional 8051 devices that execute an instruction every twelve clock cycles. With
clock speeds of up to 200 MHz, this device is an 8051 performance leader.The TSCR8051 features 128KBKBytes of partitionable Data and Program memory and extended 32-bit capabilities
including an IEEE 754-compliant floating-point coprocessor with comparator, a multiply/divide unit, a population counter,
and a leading-zero counter. 2. FeaturesIndustry standard 8051 / 8031 software compatible
RISC architecture with up to x12 speed advantage / MHz over traditional 8051 family devicesFour speed grades: 100, 150, 180, and 200 MHz
128KB of additional high-speed SRAM memory
IEEE 754-compliant floating point coprocessor for full arithmetic capabilities - up to 100 MFlops Extended 32-bit computing functions including population counter, leading zero counter, and floating-point comparatorDual data pointers for fast data block moves
Full 8051-compatible architecture including:
o Four 8-bit bi-directional ports o 256 Bytes of "Scratch Pad" memory o Three 16-bit timer/counters o Interrupt controller with 12 interrupt sources and 4 priority levels o 15-bit programmable watchdog timer o Core 8-bit arithmetic logic unit and 16-bit multiplication division unit o Two full-duplex serial ports o Four capture/compare units to generate pulse width modulated signals o Special Function Register (SFR) interface, serving up to 50 SFR devices 3. Part NumberingOptions Marking
Packages:
44 PLCC xxxxx
68 PLCC xxxxx
100 TQFP xxxxx
Operating Temperature:
Standard, 0º to 70º C S
Extended (planned) E
Speed Grade:
66 MHz -06
100 MHz -10
150 MHz -15
180 MHz -18
200 MHz -20
Part number example: TSCxxxxxPS-06 4. Operating Voltages V DDQ, V DDQF = 3.3 ± .3 VDC V DD = 1.8 ± .2 VDC DraftTSCR8051
Rev. 0.1 - June 8, 2010 Page 2 of 60 © Tezzaron Semiconductor CorporationFigure 1: Block Diagram
SRAM DataMemoryProgram
Memory
Extended
Computing
FunctionsFloating
PointUnitSPI
Memory
LoaderMemory
ControlTimers
Interrupt
Service
Register
Bidirectional
DataPorts256 Byte
Scratch Pad
Memory
Scratch Pad /
SFRControl
ALUMultiply
Divide
UnitSerial
PortsPulse Width
Modulator
UnitWatchdog
TimerRISC 8051 Microcontroller Core
Core Internal SFR Bus
TSCR8051 Functions
SFR Bus
5. Table of Contents
1. Description ......................................................... 1
2. Features ............................................................. 1
3. Part Numbering .................................................. 1
4. Operating Voltages ............................................ 1
5. Table of Contents ............................................... 2
6. Table of Figures ................................................. 2
7. Table of Tables .................................................. 3
8. Block Diagram .................................................... 4
9. Pin-Out ............................................................... 4
10. Special Function Registers ................................ 9
11. Memory ............................................................ 32
12. Instruction Set .................................................. 34
13. External SFR Timing ........................................ 42
14. Hardware Overview .......................................... 43
15. Core Engine ..................................................... 43
16. Multiplication / Division Unit (MDU) ................. 43
17. Timers .............................................................. 45
18. Serial Ports ...................................................... 51
19. Interrupts .......................................................... 54
20. Floating Point Unit (FPU) ................................. 57
21. Extended Computing Functions....................... 57
22. SPI Memory Loader ......................................... 58
23. Reset Control ................................................... 58
24. Power Management ......................................... 58
25. Device Specifications ....................................... 59
26. Package Dimensions ....................................... 59
27. Document History ............................................ 60
6. Table of Figures
Figure 1: Block Diagram ......................................................................................................................................................... 2
Figure 2: 44 PPLC, Top View .................................................................................................................................................. 4
Advance Data
TSCR8051
Special Function Register Descriptions (Continued) Rev. 0.1 - June 8, 2010 Page 3 of 60 © Tezzaron Semiconductor CorporationFigure 3 - Scratch Pad Memory ........................................................................................................................................... 32
Figure 4 - SRAM Memory Layout ......................................................................................................................................... 33
Figure 5 - External Use of Special Function Register Bus (read) ........................................................................................ 42
Figure 6 - External Use of Special Function Register Bus (write) ........................................................................................ 42
Figure 7 - Timer/Counter 1 in Mode 0 .................................................................................................................................. 46
Figure 8 - Timer/Counter 1 in Mode 2 .................................................................................................................................. 47
Figure 9 - Timer/Counter 0 in Mode 3 .................................................................................................................................. 47
Figure 10 - Timer 2 as Gated Timer: Prescaler Select = 1, Reload Mode = 1 ..................................................................... 49
Figure 11 - Timer 2 as Counter: Capture Mode = 0 (using CC3) ......................................................................................... 50
Figure 12 - Timer 2: Reload Mode = 0, Compare Mode = 0 (using CC2) ............................................................................ 50
Figure 13 - Receive Timing, Mode 0 .................................................................................................................................... 52
Figure 14 - Receive Timing, Modes 1 and B ........................................................................................................................ 53
Figure 15 - Receive Timing, Modes 2, 3, and A ................................................................................................................... 53
Figure 16 - Transmit Timing, Mode 0 ................................................................................................................................... 53
Figure 17 - Transmit Timing, Modes 1 and B ....................................................................................................................... 53
Figure 18 - Transmit Timing, Modes 2, 3, and A .................................................................................................................. 54
Figure 19 - Interrupt Processing ........................................................................................................................................... 56