Digital Core DP8051XP Data Sheet

213216 All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. DDPP 88
00 55
11 XX PP

Pipelined High Performance

8-bit Microcontroller

ver 3.10

OVERVIEW

DP8051XP is a ultra high performance,

speed optimized soft core of a single-chip 8- bit embedded controller dedicated for opera- tion with fast (typically on-chip) and slow (off- chip) memories. The core has been designed with a special concern about performance to power consumption ratio. This ratio is ex- tended by an advanced power management unit PMU.

DP8051XP soft core is 100% binary-

compatible with the industry standard 8051 8- bit microcontroller. There are two configura- tions of DP8051XP: Harward where internal data and program buses are separated, and von Neumann with common program and ex- ternal data bus. DP8051XP has Pipelined

RISC architecture 10 times faster compared

to standard architecture and executes 85-200 million instructions per second. This per- formance can also be exploited to great advan- tage in low power applications where the core can be clocked over ten times more slowly than the original implementation for no per- formance penalty.

DP8051XP is fully customizable, which

means it is delivered in the exact configuration to meet users' requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC de- sign flow. CPU FEATURES standard 8051 execute instructions 10 times faster com- pared to standard 8051 blocks copying ż Advanced INC & DEC modes

ż Auto-switch of current DPTR

Memory

external (off-chip) Program Memory

Memory

States solution for wide range of memories

speed

Wait States solution for wide range of

memories speed easy connection to memory All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. writes.

Registers

design with positive edge clocking and no internal tri-states technological process

PERIPHERALS

ż Processor execution control

Run Halt

Step into instruction

Skip instruction

Read-write all processor contents

Program Counter (PC)

Program Memory

Internal (direct) Data Memory

Special Function Registers (SFRs)

External Data Memory

Hardware execution breakpoints

Program Memory

Internal (direct) Data Memory

Special Function Registers (SFRs)

External Data Memory

Hardware breakpoints activated at a certain

Program address (PC)

Address by any write into memory

Address by any read from memory

Address by write into memory a required data

Address by read from memory a required data

Three wire communication interface

ż Power management mode

ż Switchback feature

ż Stop mode

ż 2 priority levels

ż Up to 7 external interrupt sources

ż Up to 8 interrupt sources from peripherals

ż Bit addressable data direction for each line

ż Read/write of single line and 8-bit group

ż Timers clocked by internal source

ż Auto reload 8/16-bit timers

ż Externally gated event counters

ż Synchronous mode, fixed baud rate

ż 8-bit asynchronous mode, fixed baud rate

ż 9-bit asynchronous mode, fixed baud rate

ż 9-bit asynchronous mode, variable baud rate

ż 7-bit and 10-bit addressing modes

ż NORMAL, FAST, HIGH speeds

ż Multi-master systems supported

ż Clock arbitration and synchronization

ż User defined timings on I2C lines

ż Wide range of system clock frequencies

ż Interrupt generation

ż NORMAL speed 100 kbs

ż FAST speed 400 kbs

ż HIGH speed 3400 kbs

ż Wide range of system clock frequencies

ż User defined data setup time on I2C lines

ż Interrupt generation

Interface

ż Supports speeds up ¼ of system clock

Mode fault error

Write collision error

Four transfer formats supported

ż System errors detection

ż Allows operation from a wide range of system

clock frequencies (build-in 5-bit timer)

ż Interrupt generation

ż Events capturing

All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.

ż Pulses generation

ż Digital signals generation

ż Gated timers

ż Sophisticated comparator

ż Pulse width modulation

ż Pulse width measuring

ż Multiplication - 16bit * 16bit

ż Division - 32bit / 16bit

ż Division - 16bit / 16bit

ż Left and right shifting - 1 to 31 bits

ż Normalization

IEEE-754 standard single precision

ż FADD, FSUB - addition, subtraction

ż FMUL, FDIV- multiplication, division

ż FSQRT- square root

ż FUCOM - compare

ż FCHS - change sign

ż FABS - absolute value

754 standard single precision real, word

and short integers

ż FADD, FSUB- addition, subtraction

ż FMUL, FDIV- multiplication, division

ż FSQRT- square root

ż FUCOM- compare

ż FCHS - change sign

ż FABS - absolute value

ż FSIN, FCOS- sine, cosine

ż FTAN, FATAN- tangent, arcs tangent

CONFIGURATION

The following parameters of the DP8051XP

core can be easy adjusted to requirements of dedicated application and technology. Configu- ration of the core can be prepared by effortless changing appropriate constants in package file.

There is no need to change any parts of the

code. - synchronous debug unit - unused

Besides mentioned above parameters all

available peripherals and external interrupts can be excluded from the core by changing appropriate constants in package file.

DELIVERABLES

VHDL Source Code or/and

VERILOG Source Code or/and

Encrypted, or plain text EDIF netlist

Active-HDL automatic simulation macros

ModelSim automatic simulation macros

Tests with reference responses

Installation notes

HDL core specification

Datasheet

All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. DDPP 88
00 55
11 XX PP

Pipelined High Performance

8-bit Microcontroller

ver 3.10

OVERVIEW

DP8051XP is a ultra high performance,

speed optimized soft core of a single-chip 8- bit embedded controller dedicated for opera- tion with fast (typically on-chip) and slow (off- chip) memories. The core has been designed with a special concern about performance to power consumption ratio. This ratio is ex- tended by an advanced power management unit PMU.

DP8051XP soft core is 100% binary-

compatible with the industry standard 8051 8- bit microcontroller. There are two configura- tions of DP8051XP: Harward where internal data and program buses are separated, and von Neumann with common program and ex- ternal data bus. DP8051XP has Pipelined

RISC architecture 10 times faster compared

to standard architecture and executes 85-200 million instructions per second. This per- formance can also be exploited to great advan- tage in low power applications where the core can be clocked over ten times more slowly than the original implementation for no per- formance penalty.

DP8051XP is fully customizable, which

means it is delivered in the exact configuration to meet users' requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC de- sign flow. CPU FEATURES standard 8051 execute instructions 10 times faster com- pared to standard 8051 blocks copying ż Advanced INC & DEC modes

ż Auto-switch of current DPTR

Memory

external (off-chip) Program Memory

Memory

States solution for wide range of memories

speed

Wait States solution for wide range of

memories speed easy connection to memory All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. writes.

Registers

design with positive edge clocking and no internal tri-states technological process

PERIPHERALS

ż Processor execution control

Run Halt

Step into instruction

Skip instruction

Read-write all processor contents

Program Counter (PC)

Program Memory

Internal (direct) Data Memory

Special Function Registers (SFRs)

External Data Memory

Hardware execution breakpoints

Program Memory

Internal (direct) Data Memory

Special Function Registers (SFRs)

External Data Memory

Hardware breakpoints activated at a certain

Program address (PC)

Address by any write into memory

Address by any read from memory

Address by write into memory a required data

Address by read from memory a required data

Three wire communication interface

ż Power management mode

ż Switchback feature

ż Stop mode

ż 2 priority levels

ż Up to 7 external interrupt sources

ż Up to 8 interrupt sources from peripherals

ż Bit addressable data direction for each line

ż Read/write of single line and 8-bit group

ż Timers clocked by internal source

ż Auto reload 8/16-bit timers

ż Externally gated event counters

ż Synchronous mode, fixed baud rate

ż 8-bit asynchronous mode, fixed baud rate

ż 9-bit asynchronous mode, fixed baud rate

ż 9-bit asynchronous mode, variable baud rate

ż 7-bit and 10-bit addressing modes

ż NORMAL, FAST, HIGH speeds

ż Multi-master systems supported

ż Clock arbitration and synchronization

ż User defined timings on I2C lines

ż Wide range of system clock frequencies

ż Interrupt generation

ż NORMAL speed 100 kbs

ż FAST speed 400 kbs

ż HIGH speed 3400 kbs

ż Wide range of system clock frequencies

ż User defined data setup time on I2C lines

ż Interrupt generation

Interface

ż Supports speeds up ¼ of system clock

Mode fault error

Write collision error

Four transfer formats supported

ż System errors detection

ż Allows operation from a wide range of system

clock frequencies (build-in 5-bit timer)

ż Interrupt generation

ż Events capturing

All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.

ż Pulses generation

ż Digital signals generation

ż Gated timers

ż Sophisticated comparator

ż Pulse width modulation

ż Pulse width measuring

ż Multiplication - 16bit * 16bit

ż Division - 32bit / 16bit

ż Division - 16bit / 16bit

ż Left and right shifting - 1 to 31 bits

ż Normalization

IEEE-754 standard single precision

ż FADD, FSUB - addition, subtraction

ż FMUL, FDIV- multiplication, division

ż FSQRT- square root

ż FUCOM - compare

ż FCHS - change sign

ż FABS - absolute value

754 standard single precision real, word

and short integers

ż FADD, FSUB- addition, subtraction

ż FMUL, FDIV- multiplication, division

ż FSQRT- square root

ż FUCOM- compare

ż FCHS - change sign

ż FABS - absolute value

ż FSIN, FCOS- sine, cosine

ż FTAN, FATAN- tangent, arcs tangent

CONFIGURATION

The following parameters of the DP8051XP

core can be easy adjusted to requirements of dedicated application and technology. Configu- ration of the core can be prepared by effortless changing appropriate constants in package file.

There is no need to change any parts of the

code. - synchronous debug unit - unused

Besides mentioned above parameters all

available peripherals and external interrupts can be excluded from the core by changing appropriate constants in package file.

DELIVERABLES

VHDL Source Code or/and

VERILOG Source Code or/and

Encrypted, or plain text EDIF netlist

Active-HDL automatic simulation macros

ModelSim automatic simulation macros

Tests with reference responses

Installation notes

HDL core specification

Datasheet

All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.